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https://github.com/feyisay07/meta-bsp-imx8mm.git
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37 lines
1.9 KiB
Diff
37 lines
1.9 KiB
Diff
From 0a9c14878c90919628fa76ca098f18c86c06cf97 Mon Sep 17 00:00:00 2001
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From: Valentin Raevsky <valentin@compulab.co.il>
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Date: Mon, 20 Jul 2020 13:01:28 +0300
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Subject: [PATCH 066/126] imx8m-mini: ddr: Change the memory presets order
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Make the simplest one 1-st.
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Nanya 1G has the best ddr-phy settings for reading the mr4-mr8 registers.
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Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
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---
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board/compulab/plat/imx8mm/ddr/ddr.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/board/compulab/plat/imx8mm/ddr/ddr.c b/board/compulab/plat/imx8mm/ddr/ddr.c
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index 1340475bef..4d774835ef 100644
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--- a/board/compulab/plat/imx8mm/ddr/ddr.c
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+++ b/board/compulab/plat/imx8mm/ddr/ddr.c
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@@ -63,11 +63,11 @@ struct lpddr4_desc {
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#define DEFAULT (('D' << 24) + ('E' << 16 ) + ( 'F' << 8 ) + 'A')
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static const struct lpddr4_desc lpddr4_array[] = {
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- { .name = "Micron", .id = 0xff020008, .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008}, //Only the first timing entry is in use
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- { .name = "Micron", .id = 0xff000110, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
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- { .name = "Samsung",.id = 0x01061010, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
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+ { .name = "Nanya", .id = 0x01050008, .size = 1024, .count = 1, .timing = &ucm_dram_timing_01050008}, //Only the first timing entry is in use
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{ .name = "Nanya", .id = 0x05000010, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
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- { .name = "Nanya", .id = 0x01050008, .size = 1024, .count = 1, .timing = &ucm_dram_timing_01050008},
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+ { .name = "Samsung",.id = 0x01061010, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
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+ { .name = "Micron", .id = 0xff020008, .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
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+ { .name = "Micron", .id = 0xff000110, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
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};
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static unsigned int lpddr4_get_mr(void)
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--
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2.11.0
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