mirror of
https://github.com/feyisay07/meta-bsp-imx8mm.git
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107 lines
3.5 KiB
Diff
107 lines
3.5 KiB
Diff
From 2ccda2a6956bfaa460fd871a5ba95ccb17ac5b6a Mon Sep 17 00:00:00 2001
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From: Valentin Raevsky <valentin@compulab.co.il>
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Date: Wed, 24 Apr 2019 13:55:44 +0300
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Subject: [PATCH 019/126] ucm-imx8m-mini: lpddr4_timing: Add ucm-imx8m-mini
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support
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Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
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---
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board/compulab/ucm-imx8m-mini/lpddr4_timing.c | 39 +++++++++++++++------------
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1 file changed, 22 insertions(+), 17 deletions(-)
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diff --git a/board/compulab/ucm-imx8m-mini/lpddr4_timing.c b/board/compulab/ucm-imx8m-mini/lpddr4_timing.c
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index 9c80caea8b..dfd68ea9d8 100644
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--- a/board/compulab/ucm-imx8m-mini/lpddr4_timing.c
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+++ b/board/compulab/ucm-imx8m-mini/lpddr4_timing.c
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@@ -4,34 +4,39 @@
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/kernel.h>
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-#include <asm/arch/ddr_memory_map.h>
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+#include <common.h>
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+#include <asm/arch/ddr.h>
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#include <asm/arch/lpddr4_define.h>
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#include <asm/arch/imx8m_ddr.h>
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+#undef LPDDR4_CS
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+#define LPDDR4_CS 0x3
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+
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struct dram_cfg_param lpddr4_ddrc_cfg[] = {
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/* Start to config, default 3200mbps */
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{ DDRC_DBG1(0), 0x00000001 },
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{ DDRC_PWRCTL(0), 0x00000001 },
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- { DDRC_MSTR(0), 0xa1080020 },
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+ { DDRC_MSTR(0), 0xa3080020 },
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{ DDRC_RFSHTMG(0), 0x005b00d2 },
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- { DDRC_INIT0(0), 0xC003061B },
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- { DDRC_INIT1(0), 0x009D0000 },
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+ { DDRC_INIT0(0), 0xC00305BA },
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+ { DDRC_INIT1(0), 0x00940000 },
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{ DDRC_INIT3(0), 0x00D4002D },
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{ DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 },
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- { DDRC_INIT6(0), 0x0066004a },
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- { DDRC_INIT7(0), 0x0006004a },
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+ { DDRC_INIT6(0), 0x0066004d },
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+ { DDRC_INIT7(0), 0x0016004d },
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- { DDRC_DRAMTMG0(0), 0x1A201B22 },
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- { DDRC_DRAMTMG1(0), 0x00060633 },
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- { DDRC_DRAMTMG3(0), 0x00C0C000 },
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- { DDRC_DRAMTMG4(0), 0x0F04080F },
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+ { DDRC_DRAMTMG0(0), 0x191e1920 },
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+ { DDRC_DRAMTMG1(0), 0x00060630 },
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+ { DDRC_DRAMTMG2(0), 0x070e1617},
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+ { DDRC_DRAMTMG3(0), 0x00b0b000},
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+ { DDRC_DRAMTMG4(0), 0x0e04080e},
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{ DDRC_DRAMTMG5(0), 0x02040C0C },
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{ DDRC_DRAMTMG6(0), 0x01010007 },
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{ DDRC_DRAMTMG7(0), 0x00000401 },
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{ DDRC_DRAMTMG12(0), 0x00020600 },
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{ DDRC_DRAMTMG13(0), 0x0C100002 },
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- { DDRC_DRAMTMG14(0), 0x000000E6 },
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- { DDRC_DRAMTMG17(0), 0x00A00050 },
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+ { DDRC_DRAMTMG14(0), 0x000000d8 },
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+ { DDRC_DRAMTMG17(0), 0x0096004b },
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{ DDRC_ZQCTL0(0), 0x03200018 },
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{ DDRC_ZQCTL1(0), 0x028061A8 },
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@@ -52,14 +57,14 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = {
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{ DDRC_RANKCTL(0), 0x00000c99 },
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/* address mapping */
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- { DDRC_ADDRMAP0(0), 0x0000001f },
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+ { DDRC_ADDRMAP0(0), 0x00000016 },
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{ DDRC_ADDRMAP1(0), 0x00080808 },
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{ DDRC_ADDRMAP2(0), 0x00000000 },
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{ DDRC_ADDRMAP3(0), 0x00000000 },
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{ DDRC_ADDRMAP4(0), 0x00001f1f },
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{ DDRC_ADDRMAP5(0), 0x07070707 },
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- { DDRC_ADDRMAP6(0), 0x07070707 },
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- { DDRC_ADDRMAP7(0), 0x00000f0f },
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+ { DDRC_ADDRMAP6(0), 0x0f070707 },
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+ { DDRC_ADDRMAP7(0), 0x00000000 },
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/* performance setting */
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{ DDRC_SCHED(0), 0x29001701 },
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@@ -84,7 +89,7 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = {
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{ DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
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{ DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
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{ DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
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- { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
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+ { DDRC_FREQ1_DRAMTMG14(0), 0x0000001d },
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{ DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
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{ DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
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{ DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
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@@ -1966,7 +1971,7 @@ struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
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};
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/* lpddr4 timing config params on EVK board */
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-struct dram_timing_info lpddr4_timing = {
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+struct dram_timing_info dram_timing = {
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.ddrc_cfg = lpddr4_ddrc_cfg,
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.ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
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.ddrphy_cfg = lpddr4_ddrphy_cfg,
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--
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2.11.0
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