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spl: Enable Kingston DRAM support

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Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
This commit is contained in:
Kirill Kapranov
2020-08-19 18:56:30 +03:00
parent 6cdc2ece9a
commit 4e8a73ee2e
3 changed files with 152 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
recipes-bsp/u-boot/compulab/imx8mm.inc
+2
View File
@@ -79,4 +79,6 @@ SRC_URI_append = " \
file://0077-mcm-imx8m-mini-spl-Add-board_fit_config_name_match.patch \
file://0078-imx8m-mini-u-boot-Add-__weak-uboot_board_private_ini.patch \
file://0079-mcm-imx8m-mini-u-boot-Add-uboot_board_private_init.patch \
file://0080-Add-ddr_init-return-handling.patch \
file://0081-spl-Enable-Kingston-DRAM-support.patch \
"
recipes-bsp/u-boot/compulab/imx8mm/0080-Add-ddr_init-return-handling.patch
+29
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@@ -0,0 +1,29 @@
From eaf85210b4c908c054209b0091742e9b4ba229cd Mon Sep 17 00:00:00 2001
From: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Date: Wed, 19 Aug 2020 18:45:55 +0300
Subject: [PATCH 80/81] Add ddr_init return handling
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
---
board/compulab/plat/imx8mm/ddr/ddr.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/board/compulab/plat/imx8mm/ddr/ddr.c b/board/compulab/plat/imx8mm/ddr/ddr.c
index a783d16636..47252f8b57 100644
--- a/board/compulab/plat/imx8mm/ddr/ddr.c
+++ b/board/compulab/plat/imx8mm/ddr/ddr.c
@@ -150,7 +150,10 @@ void spl_dram_init(void)
printf("DDRINFO(%s): %s %dG @ %d MHz\n", (ddr_found ? "D" : "?" ), lpddr4_array[i].name,
lpddr4_array[i].size, lpddr4_array[i].timing->fsp_table[0]);
- ddr_init(lpddr4_array[i].timing);
+ if (ddr_init(lpddr4_array[i].timing)) {
+ SPL_TCM_INIT;
+ do_reset(NULL,0,0,NULL);
+ }
ddr_info_mrr = lpddr4_get_mr();
if (ddr_info_mrr == 0xFFFFFFFF ) {
--
2.11.0
recipes-bsp/u-boot/compulab/imx8mm/0081-spl-Enable-Kingston-DRAM-support.patch
+121
View File
@@ -0,0 +1,121 @@
From d2e352d3d8378b445f342720e7bd227568ea848b Mon Sep 17 00:00:00 2001
From: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Date: Tue, 18 Aug 2020 19:10:19 +0300
Subject: [PATCH 81/81] spl: Enable Kingston DRAM support
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
---
board/compulab/plat/imx8/eeprom/eeprom_spl.c | 21 +++++++++++++++++++++
board/compulab/plat/imx8mm/ddr/ddr.c | 27 ++++++++++++++++++++-------
2 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/board/compulab/plat/imx8/eeprom/eeprom_spl.c b/board/compulab/plat/imx8/eeprom/eeprom_spl.c
index 5f49a17ed8..ece6b38101 100644
--- a/board/compulab/plat/imx8/eeprom/eeprom_spl.c
+++ b/board/compulab/plat/imx8/eeprom/eeprom_spl.c
@@ -78,6 +78,10 @@ static int cl_eeprom_write(uint offset, uchar *buf, int len)
#define BOARD_DDRINFO_SIZE 4
static u32 board_ddrinfo = 0xdeadbeef;
+#define BOARD_DDRSUBIND_OFFSET 0x44
+#define BOARD_DDRSUBIND_SIZE 1
+static u8 board_ddrsubind = 0xff;
+
#define BOARD_DRATE_OFFSET 0x50
#define BOARD_DRATE_SIZE 4
static u32 board_drate = 0xdeadbeef;
@@ -128,6 +132,23 @@ u32 cl_eeprom_set_drate(u32 drate, unsigned int r, unsigned int c)
return board_drate;
};
+u8 cl_eeprom_get_subind(void)
+{
+ if (cl_eeprom_read(BOARD_DDRSUBIND_OFFSET, (uchar *)&board_ddrsubind, BOARD_DDRSUBIND_SIZE))
+ return 0xff;
+
+ return board_ddrsubind;
+};
+
+u8 cl_eeprom_set_subind(u8 ddrsubind)
+{
+ if (cl_eeprom_write(BOARD_DDRSUBIND_OFFSET, (uchar *)&ddrsubind, BOARD_DDRSUBIND_SIZE))
+ return 0xff;
+ board_ddrsubind = ddrsubind;
+
+ return board_ddrsubind;
+};
+
/* override-size ifaces */
u32 cl_eeprom_get_osize(void)
{
diff --git a/board/compulab/plat/imx8mm/ddr/ddr.c b/board/compulab/plat/imx8mm/ddr/ddr.c
index 47252f8b57..1a7e5c168a 100644
--- a/board/compulab/plat/imx8mm/ddr/ddr.c
+++ b/board/compulab/plat/imx8mm/ddr/ddr.c
@@ -17,6 +17,8 @@
/* Forward declarations */
u32 cl_eeprom_get_ddrinfo(void);
u32 cl_eeprom_set_ddrinfo(u32 ddrinfo);
+u32 cl_eeprom_get_subind(void);
+u32 cl_eeprom_set_subind(u32 subind);
u32 cl_eeprom_get_osize(void);
@@ -55,17 +57,24 @@ struct lpddr4_desc {
* use it if default is not the
* 1-st array entry */
unsigned int _default;
+ /* An optional field to distiguish DRAM chips that
+ * have different geometry, though return the same MRR.
+ * Default value 0xff
+ */
+ u8 subind;
struct dram_timing_info *timing;
char *desc[4];
};
#define DEFAULT (('D' << 24) + ('E' << 16 ) + ( 'F' << 8 ) + 'A')
static const struct lpddr4_desc lpddr4_array[] = {
- { .name = "Nanya", .id = 0x01050008, .size = 1024, .count = 1, .timing = &ucm_dram_timing_01050008}, //Only the first timing entry is in use
- { .name = "Nanya", .id = 0x05000010, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
- { .name = "Samsung",.id = 0x01061010, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
- { .name = "Micron", .id = 0xff020008, .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
- { .name = "Micron", .id = 0xff000110, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+ { .name = "Nanya", .id = 0x05000010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+ { .name = "Samsung", .id = 0x01061010, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+ { .name = "Samsung", .id = 0x01050008, .subind = 0xff, .size = 1024, .count = 1, .timing = &ucm_dram_timing_01050008},
+ { .name = "Kingston", .id = 0xff000010, .subind = 0x04, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
+ { .name = "Kingston", .id = 0xff000010, .subind = 0x02, .size = 2048, .count = 1, .timing = &ucm_dram_timing_01061010},
+ { .name = "Micron", .id = 0xff020008, .subind = 0xff, .size = 2048, .count = 1, .timing = &ucm_dram_timing_ff020008},
+ { .name = "Micron", .id = 0xff000110, .subind = 0xff, .size = 4096, .count = 1, .timing = &ucm_dram_timing_ff000110},
};
static unsigned int lpddr4_get_mr(void)
@@ -120,7 +129,8 @@ void spl_dram_init(void)
/* get ddr type from the eeprom if not in tcm scan mode */
ddr_info = cl_eeprom_get_ddrinfo();
for ( i = 0; i < ARRAY_SIZE(lpddr4_array); i++ ) {
- if (lpddr4_array[i].id == ddr_info) {
+ if (lpddr4_array[i].id == ddr_info &&
+ lpddr4_array[i].subind == cl_eeprom_get_subind()) {
ddr_found = 1;
break;
}
@@ -175,10 +185,13 @@ void spl_dram_init(void)
if (ddr_found == 0) {
/* Update eeprom */
cl_eeprom_set_ddrinfo(ddr_info_mrr);
+ mdelay(10);
ddr_info = cl_eeprom_get_ddrinfo();
+ mdelay(10);
+ cl_eeprom_set_subind(lpddr4_array[i].subind);
/* make sure that the ddr_info has reached the eeprom */
printf("DDRINFO(E): mr5-8 [ 0x%x ], read back\n", ddr_info);
- if (ddr_info_mrr != ddr_info) {
+ if (ddr_info_mrr != ddr_info || cl_eeprom_get_subind() != lpddr4_array[i].subind) {
printf("DDRINFO(EEPROM): make sure that the eeprom is accessible\n");
printf("DDRINFO(EEPROM): i2c dev 1; i2c md 0x51 0x40 0x50\n");
}
--
2.11.0