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iot-gate-imx8: u-boot: Enable phy Realtek RTL8211E

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Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
This commit is contained in:
Valentin Raevsky
2023-04-22 13:58:24 +03:00
parent 12fd0a9ecb
commit 2d14ae60e4
2 changed files with 176 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
recipes-bsp/u-boot/compulab/imx8mm.inc
+1
View File
@@ -105,4 +105,5 @@ SRC_URI_append = " \
file://0103-iot-gate-imx8-add-support-for-the-IE-TPM-module.patch \
file://0104-iot-gate-imx8-add-support-for-the-IE-POE-extension-b.patch \
file://0105-release-2020.04-iot-gate-imx8-2.2.patch \
file://0106-imx8mm-net-enable-phy-Realtek-RTL8211E.patch \
"
recipes-bsp/u-boot/compulab/imx8mm/0106-imx8mm-net-enable-phy-Realtek-RTL8211E.patch
+175
View File
@@ -0,0 +1,175 @@
From 7790ade5c3055752fdb12adfc5bf14a719517706 Mon Sep 17 00:00:00 2001
From: Valentin Raevsky <valentin@compulab.co.il>
Date: Sat, 22 Apr 2023 13:55:28 +0300
Subject: [PATCH] imx8mm: net: enable phy Realtek RTL8211E
Developed the infrastructure for further enablement of an ethernet phy.
Phy's ID is read directly from the phy to distinguish vendor/model and apply
an appropriate tuning.
TBD: support of multiple phys on single bus shall be added.
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Signed-off-by: Valentin Raevsky <valentin@compulab.co.il>
%% original patch: 0125-imx8mm-net-enable-phy-Realtek-RTL8211E.patch
---
board/compulab/plat/imx8mm/board/board.c | 106 +++++++++++++++++++++--
include/configs/cpl-imx8m-mini.h | 2 +-
2 files changed, 99 insertions(+), 9 deletions(-)
diff --git a/board/compulab/plat/imx8mm/board/board.c b/board/compulab/plat/imx8mm/board/board.c
index e9ea89886f..88b6e5bd56 100644
--- a/board/compulab/plat/imx8mm/board/board.c
+++ b/board/compulab/plat/imx8mm/board/board.c
@@ -31,9 +31,15 @@
#include "ddr/ddr.h"
#include "common/eeprom.h"
#include "common/rtc.h"
+#include <asm-generic/u-boot.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
+static int env_dev = -1;
+static int env_part= -1;
+static int fec_phyaddr = -1;
+
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{
@@ -127,9 +133,21 @@ __weak int sub_ft_board_setup(void *blob, bd_t *bd)
return 0;
}
+#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0"
+#define FLIP_32B(val) (((val>>24)&0xff) | ((val<<8)&0xff0000) | ((val>>8)&0xff00) | ((val<<24)&0xff000000))
+static int fdt_set_fec_phy_addr(void *blob)
+{
+ if(0 > fec_phyaddr)
+ return -EINVAL;
+
+ u32 val = FLIP_32B(fec_phyaddr);
+ return fdt_find_and_setprop
+ (blob, FDT_PHYADDR, "reg", (const void*)&val, sizeof(val), 0);
+}
int ft_board_setup(void *blob, bd_t *bd)
{
fdt_set_sn(blob);
+ fdt_set_fec_phy_addr(blob);
return sub_ft_board_setup(blob, bd);
return 0;
@@ -195,16 +213,88 @@ static int setup_fec(void)
return set_clk_enet(ENET_125MHZ);
}
+/* These are specifc ID, purposed to distiguish between PHY vendors.
+These values are not equal to real vendors' OUI (half of MAC address) */
+#define OUI_PHY_ATHEROS 0x1374
+#define OUI_PHY_REALTEK 0x0732
+
int board_phy_config(struct phy_device *phydev)
{
- /* enable rgmii rxc skew and phy mode select to RGMII copper */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
-
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+ int phyid1, phyid2;
+ unsigned int model, rev, oui;
+ unsigned int reg;
+
+ phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
+ if(0 > phyid1) {
+ printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1);
+ return phyid1;
+ }
+
+ phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
+ if(0 > phyid2) {
+ printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2);
+ return phyid2;
+ }
+
+ reg = phyid2 | phyid1 << 16;
+ if(0xffff == reg) {
+ printf("%s: There is no device @%i\n", __func__, phydev->addr);
+ return -ENODEV;
+ }
+
+ rev = reg & 0xf;
+ reg >>= 4;
+ model = reg & 0x3f;
+ reg >>=6;
+ oui = reg;
+ debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+
+ switch (oui) {
+ case OUI_PHY_ATHEROS:
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ printf("phy: AR803x@%x\t", phydev->addr);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+ break;
+ case OUI_PHY_REALTEK:
+ printf("phy: RTL8211E@%x\t", phydev->addr);
+ /** RTL8211E-VB-CG - add TX and RX delay */
+ unsigned short val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c);
+ val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val);
+ /*LEDs:*/
+ /* set to extension page */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007);
+ /* extension Page44 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR
+ /* To disable EEE LED mode (blinking .4s/2s) */
+ /* extension Page5 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0
+
+ break;
+ default:
+ printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+ return -ENOSYS;
+ }
+
+ fec_phyaddr = phydev->addr;
if (phydev->drv->config)
phydev->drv->config(phydev);
diff --git a/include/configs/cpl-imx8m-mini.h b/include/configs/cpl-imx8m-mini.h
index 90ca1e6138..ed76cdcf84 100644
--- a/include/configs/cpl-imx8m-mini.h
+++ b/include/configs/cpl-imx8m-mini.h
@@ -74,7 +74,7 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_FEC_MXC_PHYADDR -1 /*Auto search of PHY on MII*/
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE
--
2.17.1