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net: Enable phy Realtek RTL8211E

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Introduce an infrastructure for enablement of Ethernet phy by means of reading
ID directly from the phy to distinguish between models of the phy, then apply
an appropriate fine tuning.

TBD: support of multiple phys on single bus shall be added.

Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
This commit is contained in:
Kirill Kapranov
2022-02-28 22:17:53 +02:00
parent ee920c5511
commit 0927d04f9d
6 changed files with 268 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
recipes-bsp/u-boot/compulab/imx8mm.inc
+2
View File
@@ -102,4 +102,6 @@ SRC_URI_append = " \
file://0101-spl-Enable-Samsung-4G-DRAM-0x01061010.patch \
file://0102-Enable-DDR-Alliance-1G-0x01050008.patch \
file://0103-make-Add-wrapper-for-compound-config.patch \
file://0104-net-Enable-phy-Realtek-RTL8211E.patch \
file://0105-LOCALVERSION-2.2.1-1.1.1.patch \
"
recipes-bsp/u-boot/compulab/imx8mm/0104-net-Enable-phy-Realtek-RTL8211E.patch
+181
View File
@@ -0,0 +1,181 @@
From 3571fbae5cba75df92f1ec2c1f1011949ca82ab7 Mon Sep 17 00:00:00 2001
From: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Date: Tue, 1 Feb 2022 23:25:01 +0200
Subject: [PATCH 104/105] net: Enable phy Realtek RTL8211E
Developed the infrastructure for further enablement of an ethernet phy. Phy's
ID is read directly from the phy to distinguish vendor/model and apply an
appropriate tuning.
TBD: support of multiple phys on single bus shall be added.
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
---
board/compulab/plat/imx8mm/board/board.c | 105 ++++++++++++++++++++++++++++---
include/configs/cpl-imx8m-mini.h | 2 +-
2 files changed, 97 insertions(+), 10 deletions(-)
diff --git a/board/compulab/plat/imx8mm/board/board.c b/board/compulab/plat/imx8mm/board/board.c
index 3ce1659c61..e6b41ea5e5 100644
--- a/board/compulab/plat/imx8mm/board/board.c
+++ b/board/compulab/plat/imx8mm/board/board.c
@@ -3,7 +3,6 @@
*
* SPDX-License-Identifier: GPL-2.0+
*/
-
#include <common.h>
#include <malloc.h>
#include <errno.h>
@@ -34,11 +33,14 @@
#include "ddr/ddr.h"
#include "common/eeprom.h"
#include "common/rtc.h"
+#include <asm-generic/u-boot.h>
+#include <fdt_support.h>
DECLARE_GLOBAL_DATA_PTR;
static int env_dev = -1;
static int env_part= -1;
+static int fec_phyaddr = -1;
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
@@ -151,10 +153,23 @@ static int fdt_set_env_addr(void *blob)
return 0;
}
+#define FDT_PHYADDR "/soc@0/bus@30800000/ethernet@30be0000/mdio/ethernet-phy@0"
+#define FLIP_32B(val) (((val>>24)&0xff) | ((val<<8)&0xff0000) | ((val>>8)&0xff00) | ((val<<24)&0xff000000))
+static int fdt_set_fec_phy_addr(void *blob)
+{
+ if(0 > fec_phyaddr)
+ return -EINVAL;
+
+ u32 val = FLIP_32B(fec_phyaddr);
+ return fdt_find_and_setprop
+ (blob, FDT_PHYADDR, "reg", (const void*)&val, sizeof(val), 0);
+}
+
int ft_board_setup(void *blob, struct bd_info *bd)
{
fdt_set_env_addr(blob);
fdt_set_sn(blob);
+ fdt_set_fec_phy_addr(blob);
return 0;
}
#endif
@@ -218,16 +233,88 @@ static int setup_fec(void)
return set_clk_enet(ENET_125MHZ);
}
+/* These are specifc ID, purposed to distiguish between PHY vendors.
+These values are not equal to real vendors' OUI (half of MAC address) */
+#define OUI_PHY_ATHEROS 0x1374
+#define OUI_PHY_REALTEK 0x0732
+
int board_phy_config(struct phy_device *phydev)
{
- /* enable rgmii rxc skew and phy mode select to RGMII copper */
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
-
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
- phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+ int phyid1, phyid2;
+ unsigned int model, rev, oui;
+ unsigned int reg;
+
+ phyid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1);
+ if(0 > phyid1) {
+ printf("%s: PHYID1 registry read fail %i\n", __func__, phyid1);
+ return phyid1;
+ }
+
+ phyid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2);
+ if(0 > phyid2) {
+ printf("%s: PHYID2 registry read fail %i\n", __func__, phyid2);
+ return phyid2;
+ }
+
+ reg = phyid2 | phyid1 << 16;
+ if(0xffff == reg) {
+ printf("%s: There is no device @%i\n", __func__, phydev->addr);
+ return -ENODEV;
+ }
+
+ rev = reg & 0xf;
+ reg >>= 4;
+ model = reg & 0x3f;
+ reg >>=6;
+ oui = reg;
+ debug("%s: PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+
+ switch (oui) {
+ case OUI_PHY_ATHEROS:
+ /* enable rgmii rxc skew and phy mode select to RGMII copper */
+ printf("phy: AR803x@%x\t", phydev->addr);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
+ break;
+ case OUI_PHY_REALTEK:
+ printf("phy: RTL8211E@%x\t", phydev->addr);
+ /** RTL8211E-VB-CG - add TX and RX delay */
+ unsigned short val;
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x07);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0xa4);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1c);
+ val |= (0x1 << 13) | (0x1 << 12) | (0x1 << 11);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, val);
+ /*LEDs:*/
+ /* set to extension page */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0007);
+ /* extension Page44 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x002c);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1c, 0x0430);//LCR
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1a, 0x0010);//LACR
+ /* To disable EEE LED mode (blinking .4s/2s) */
+ /* extension Page5 */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x0005);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x05, 0x8b82);//magic const
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x06, 0x052b);//magic const
+
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x00);// Back to Page0
+
+ break;
+ default:
+ printf("%s: ERROR: unknown PHY @0x%x OUI 0x%06x model 0x%x rev 0x%x\n",
+ __func__, phydev->addr, oui, model, rev);
+ return -ENOSYS;
+ }
+
+ fec_phyaddr = phydev->addr;
if (phydev->drv->config)
phydev->drv->config(phydev);
diff --git a/include/configs/cpl-imx8m-mini.h b/include/configs/cpl-imx8m-mini.h
index 9ef84842d0..4dd7142cbd 100644
--- a/include/configs/cpl-imx8m-mini.h
+++ b/include/configs/cpl-imx8m-mini.h
@@ -74,7 +74,7 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_FEC_MXC_PHYADDR 0
+#define CONFIG_FEC_MXC_PHYADDR -1 //Auto search of PHY on MII
#define FEC_QUIRK_ENET_MAC
#define CONFIG_PHY_GIGE
--
2.11.0
recipes-bsp/u-boot/compulab/imx8mm/0105-LOCALVERSION-2.2.1-1.1.1.patch
+34
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@@ -0,0 +1,34 @@
From 9ec3f941e83d2ea0d7bca961da5320f4df16ab88 Mon Sep 17 00:00:00 2001
From: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Date: Fri, 4 Feb 2022 00:35:47 +0200
Subject: [PATCH 105/105] LOCALVERSION 2.2.1/1.1.1
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
---
configs/mcm-imx8m-mini.config | 2 +-
configs/ucm-imx8m-mini.config | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/configs/mcm-imx8m-mini.config b/configs/mcm-imx8m-mini.config
index 472d4637e3..0aa9304b3f 100644
--- a/configs/mcm-imx8m-mini.config
+++ b/configs/mcm-imx8m-mini.config
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="-mcm-imx8m-mini-1.1"
+CONFIG_LOCALVERSION="-mcm-imx8m-mini-1.1.1"
CONFIG_TARGET_MCM_IMX8M_MINI=y
CONFIG_DEFAULT_DTB="mcm-imx8m-mini.dtb"
CONFIG_DEFAULT_FDT_FILE="mcm-imx8m-mini.dtb"
diff --git a/configs/ucm-imx8m-mini.config b/configs/ucm-imx8m-mini.config
index 41d00fe549..d411c1cfee 100644
--- a/configs/ucm-imx8m-mini.config
+++ b/configs/ucm-imx8m-mini.config
@@ -1,4 +1,4 @@
-CONFIG_LOCALVERSION="-ucm-imx8m-mini-2.1"
+CONFIG_LOCALVERSION="-ucm-imx8m-mini-2.2.1"
CONFIG_TARGET_UCM_IMX8M_MINI=y
CONFIG_DEFAULT_DTB="ucm-imx8m-mini.dtb"
CONFIG_DEFAULT_FDT_FILE="ucm-imx8m-mini.dtb"
--
2.11.0
recipes-kernel/linux/compulab/imx8mm.inc
+2
View File
@@ -51,5 +51,7 @@ SRC_URI_append = " \
file://0050-mcm-dts-Reorder-DTS.patch \
file://0051-mcm-imx8m-mini-dts-Fix-rtc-enumeration-order.patch \
file://0052-mcm-imx8m-mini-defconfig-Enable-CAN-mcp251x.patch \
file://0053-dts-phy-Eliminate-excessive-reset.patch \
file://0054-LOCALVERSION-2.2.1.patch \
"
recipes-kernel/linux/compulab/imx8mm/0053-dts-phy-Eliminate-excessive-reset.patch
+29
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@@ -0,0 +1,29 @@
From 168029d8d8f77e112d2fc90654a1fa867f04f1d8 Mon Sep 17 00:00:00 2001
From: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Date: Mon, 14 Feb 2022 01:14:32 +0200
Subject: [PATCH 53/54] dts:phy: Eliminate excessive reset
The eth phy is tuned on u-boot, however the reset at Linux boot cleans all the
tuning and makes the phy inoperable. Eliminate the reset at Linux boot so as to
preserve the phy tuned.
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
---
arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dtsi b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dtsi
index 377574898946..c40bc84e3e17 100644
--- a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dtsi
+++ b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dtsi
@@ -79,6 +79,7 @@
regulator-always-on;
enable-active-high;
startup-delay-us = <500>;
+ regulator-boot-on;
};
usdhc1_pwrseq: usdhc1_pwrseq {
--
2.11.0
recipes-kernel/linux/compulab/imx8mm/0054-LOCALVERSION-2.2.1.patch
+20
View File
@@ -0,0 +1,20 @@
From b676b1854cfe718a8f2f3cb236369dda45d4827f Mon Sep 17 00:00:00 2001
From: Kirill Kapranov <kirill.kapranov@compulab.co.il>
Date: Mon, 14 Feb 2022 01:20:30 +0200
Subject: [PATCH 54/54] LOCALVERSION-2.2.1
Signed-off-by: Kirill Kapranov <kirill.kapranov@compulab.co.il>
---
arch/arm64/configs/ucm-imx8m-mini.config | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/configs/ucm-imx8m-mini.config b/arch/arm64/configs/ucm-imx8m-mini.config
index 228631956437..6e050f14df35 100644
--- a/arch/arm64/configs/ucm-imx8m-mini.config
+++ b/arch/arm64/configs/ucm-imx8m-mini.config
@@ -1 +1 @@
-CONFIG_LOCALVERSION="-ucm-imx8m-mini-2.2"
+CONFIG_LOCALVERSION="-ucm-imx8m-mini-2.2.1"
--
2.11.0