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[amdgpu] Skip OR combining on 64-bit integer before legalizing ops.

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Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81710
This commit is contained in:
Michael Liao
2020-06-12 15:22:38 -04:00
parent e64059828f
commit ec02635d10
2 changed files with 2 additions and 2 deletions
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llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+1 -1
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@@ -8958,7 +8958,7 @@ SDValue SITargetLowering::performOrCombine(SDNode *N,
}
}
if (VT != MVT::i64)
if (VT != MVT::i64 || DCI.isBeforeLegalizeOps())
return SDValue();
// TODO: This could be a generic combine with a predicate for extracting the
llvm/test/CodeGen/AMDGPU/fshr.ll
+1 -1
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@@ -763,7 +763,7 @@ define <3 x i16> @v_fshr_v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2
; SI-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; SI-NEXT: v_cndmask_b32_e32 v1, v2, v5, vcc
; SI-NEXT: v_and_b32_e32 v2, v9, v1
; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16
; SI-NEXT: v_alignbit_b32 v1, v1, v0, 16
; SI-NEXT: s_setpc_b64 s[30:31]
;
; VI-LABEL: v_fshr_v3i16: