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unsigned -> Register for readability.
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@@ -619,7 +619,7 @@ bool FastISel::selectBinaryOp(const User *I, unsigned ISDOpcode) {
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// we don't have anything that canonicalizes operand order.
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if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(0)))
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if (isa<Instruction>(I) && cast<Instruction>(I)->isCommutative()) {
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unsigned Op1 = getRegForValue(I->getOperand(1));
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Register Op1 = getRegForValue(I->getOperand(1));
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if (!Op1)
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return false;
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bool Op1IsKill = hasTrivialKill(I->getOperand(1));
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@@ -1941,7 +1941,7 @@ bool FastISel::selectOperator(const User *I, unsigned Opcode) {
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return selectCast(I, ISD::ZERO_EXTEND);
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if (DstVT.bitsLT(SrcVT))
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return selectCast(I, ISD::TRUNCATE);
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unsigned Reg = getRegForValue(I->getOperand(0));
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Register Reg = getRegForValue(I->getOperand(0));
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if (!Reg)
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return false;
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updateValueMap(I, Reg);
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@@ -2071,7 +2071,7 @@ Register FastISel::constrainOperandRegClass(const MCInstrDesc &II, Register Op,
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if (!MRI.constrainRegClass(Op, RegClass)) {
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// If it's not legal to COPY between the register classes, something
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// has gone very wrong before we got here.
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unsigned NewOp = createResultReg(RegClass);
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Register NewOp = createResultReg(RegClass);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
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return NewOp;
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