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[AArch64][GlobalISel] Avoid creating redundant ubfx when selecting G_ZEXT
When selecting 32 b -> 64 b G_ZEXTs, we don't have to always emit the extend. If the instruction feeding into the G_ZEXT implicitly zero extends the high half of the register, we can just emit a SUBREG_TO_REG instead. Differential Revision: https://reviews.llvm.org/D81897
This commit is contained in:
Jessica Paquette
@@ -2605,13 +2605,44 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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// %v2(s32) = G_ZEXT %v(s8)
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if (!IsSigned) {
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auto *LoadMI = getOpcodeDef(TargetOpcode::G_LOAD, SrcReg, MRI);
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if (LoadMI &&
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RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID) {
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bool IsGPR =
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RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::GPRRegBankID;
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if (LoadMI && IsGPR) {
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const MachineMemOperand *MemOp = *LoadMI->memoperands_begin();
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unsigned BytesLoaded = MemOp->getSize();
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if (BytesLoaded < 4 && SrcTy.getSizeInBytes() == BytesLoaded)
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return selectCopy(I, TII, MRI, TRI, RBI);
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}
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// If we are zero extending from 32 bits to 64 bits, it's possible that
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// the instruction implicitly does the zero extend for us. In that case,
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// we can just emit a SUBREG_TO_REG.
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if (IsGPR && SrcSize == 32 && DstSize == 64) {
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// Unlike with the G_LOAD case, we don't want to look through copies
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// here.
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MachineInstr *Def = MRI.getVRegDef(SrcReg);
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if (Def && isDef32(*Def)) {
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MIB.buildInstr(AArch64::SUBREG_TO_REG, {DefReg}, {})
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.addImm(0)
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.addUse(SrcReg)
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.addImm(AArch64::sub_32);
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if (!RBI.constrainGenericRegister(DefReg, AArch64::GPR64RegClass,
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MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain G_ZEXT destination\n");
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return false;
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}
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if (!RBI.constrainGenericRegister(SrcReg, AArch64::GPR32RegClass,
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MRI)) {
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LLVM_DEBUG(dbgs() << "Failed to constrain G_ZEXT source\n");
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return false;
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}
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I.eraseFromParent();
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return true;
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}
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}
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}
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if (DstSize == 64) {
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@@ -59,15 +59,14 @@ body: |
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; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4, 0, implicit-def $nzcv
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64common = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $xzr = SUBSXri [[UBFMXri]], 71, 0, implicit-def $nzcv
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[SUBSWri]], %subreg.sub_32
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; CHECK: $xzr = SUBSXri [[SUBREG_TO_REG]], 71, 0, implicit-def $nzcv
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; CHECK: Bcc 8, %bb.4, implicit $nzcv
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; CHECK: bb.1.entry:
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; CHECK: successors: %bb.3(0x2aaaaaab), %bb.4(0x2aaaaaab), %bb.2(0x2aaaaaab)
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; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
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; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
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; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[UBFMXri]], %jump-table.0
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; CHECK: early-clobber %18:gpr64, early-clobber %19:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
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; CHECK: BR %18
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; CHECK: bb.2.sw.bb:
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; CHECK: successors: %bb.4(0x80000000)
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@@ -0,0 +1,204 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
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...
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---
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name: fold
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; This should not have an UBFMXri, since ADDWrr implicitly gives us the
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; zext.
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; CHECK-LABEL: name: fold
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ADDWrr]], %subreg.sub_32
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; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(s32) = G_ADD %1, %0
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%3:gpr(s64) = G_ZEXT %2(s32)
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$x0 = COPY %3(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_fold_s16
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; We should have a UBFMXri here, because we only do this for zero extends
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; from 32 bits to 64 bits.
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; CHECK-LABEL: name: dont_fold_s16
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; CHECK: liveins: $w0, $w1
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; CHECK: [[DEF:%[0-9]+]]:gpr32 = IMPLICIT_DEF
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[DEF]], %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s16) = G_IMPLICIT_DEF
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%3:gpr(s64) = G_ZEXT %0(s16)
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$x0 = COPY %3(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_fold_copy
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; We should have a UBFMXri here, because isDef32 disallows copies.
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; CHECK-LABEL: name: dont_fold_copy
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32 = COPY $w0
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %copy, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY %zext
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(s32) = COPY $w0
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%zext:gpr(s64) = G_ZEXT %copy(s32)
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$x0 = COPY %zext(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_fold_bitcast
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0
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; We should have a UBFMXri here, because isDef32 disallows bitcasts.
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; CHECK-LABEL: name: dont_fold_bitcast
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; CHECK: liveins: $w0
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; CHECK: %copy:gpr32all = COPY $w0
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; CHECK: %bitcast:gpr32 = COPY %copy
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %bitcast, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY %zext
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(s32) = COPY $w0
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%bitcast:gpr(s32) = G_BITCAST %copy(s32)
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%zext:gpr(s64) = G_ZEXT %bitcast(s32)
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$x0 = COPY %zext(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_fold_trunc
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x0
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; We should have a UBFMXri here, because isDef32 disallows truncs.
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; CHECK-LABEL: name: dont_fold_trunc
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; CHECK: liveins: $x0
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; CHECK: %copy:gpr64sp = COPY $x0
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; CHECK: %trunc:gpr32common = COPY %copy.sub_32
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %trunc, %subreg.sub_32
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; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY %zext
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; CHECK: RET_ReallyLR implicit $x0
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%copy:gpr(s64) = COPY $x0
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%trunc:gpr(s32) = G_TRUNC %copy(s64)
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%zext:gpr(s64) = G_ZEXT %trunc(s32)
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$x0 = COPY %zext(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_fold_phi
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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; CHECK-LABEL: name: dont_fold_phi
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; CHECK: bb.0:
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; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK: liveins: $w0, $w1, $w2
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; CHECK: %copy1:gpr32all = COPY $w0
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; CHECK: %copy2:gpr32all = COPY $w1
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; CHECK: %cond_wide:gpr32 = COPY $w2
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; CHECK: TBNZW %cond_wide, 0, %bb.1
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; CHECK: B %bb.2
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x80000000)
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; CHECK: bb.2:
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; CHECK: %phi:gpr32 = PHI %copy1, %bb.0, %copy2, %bb.1
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %phi, %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: RET_ReallyLR implicit $x0
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; We should have a UBFMXri here, because isDef32 disallows phis.
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bb.0:
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liveins: $w0, $w1, $w2
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%copy1:gpr(s32) = COPY $w0
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%copy2:gpr(s32) = COPY $w1
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%cond_wide:gpr(s32) = COPY $w2
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%cond:gpr(s1) = G_TRUNC %cond_wide(s32)
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G_BRCOND %cond(s1), %bb.1
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G_BR %bb.2
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bb.1:
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bb.2:
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%phi:gpr(s32) = G_PHI %copy1(s32), %bb.0, %copy2(s32), %bb.1
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%5:gpr(s64) = G_ZEXT %phi(s32)
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$x0 = COPY %5(s64)
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RET_ReallyLR implicit $x0
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...
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---
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name: dont_look_through_copy
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $w0, $w1
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; Make sure we don't walk past the copy.
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; CHECK-LABEL: name: dont_look_through_copy
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; CHECK: liveins: $w0, $w1
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
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; CHECK: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY1]], [[COPY]]
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ADDWrr]], %subreg.sub_32
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; CHECK: [[UBFMXri:%[0-9]+]]:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
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; CHECK: $x0 = COPY [[UBFMXri]]
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; CHECK: RET_ReallyLR implicit $x0
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%0:gpr(s32) = COPY $w0
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%1:gpr(s32) = COPY $w1
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%2:gpr(s32) = G_ADD %1, %0
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%3:gpr(s32) = COPY %2(s32)
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%4:gpr(s64) = G_ZEXT %3(s32)
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$x0 = COPY %4(s64)
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RET_ReallyLR implicit $x0
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