diff --git a/meta-bsp-imx8mm/conf/machine/ucm-imx8m-mini.conf b/meta-bsp-imx8mm/conf/machine/ucm-imx8m-mini.conf index 532ed80..5a679c5 100644 --- a/meta-bsp-imx8mm/conf/machine/ucm-imx8m-mini.conf +++ b/meta-bsp-imx8mm/conf/machine/ucm-imx8m-mini.conf @@ -43,3 +43,5 @@ IMX_BOOT_SEEK = "33" OPTEE_BIN_EXT = "8mm" PLATFORM_FLAVOR_ucm-imx8m-mini = "mx8mmevk" + +MACHINE_FIRMWARE += "firmware-imx-brcm" diff --git a/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state.bbappend b/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state.bbappend new file mode 100644 index 0000000..09fd714 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state.bbappend @@ -0,0 +1,3 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/${PN}:" + +PACKAGE_ARCH_mx8 = "${MACHINE_ARCH}" diff --git a/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state/mx8/asound.conf b/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state/mx8/asound.conf new file mode 100644 index 0000000..9a5800e --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state/mx8/asound.conf @@ -0,0 +1,12 @@ +pcm.device{ + format S16_LE + rate 48000 + type hw + card 0 + device 0 +} + +pcm.!default{ + type plug + slave.pcm "device" +} diff --git a/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state/mx8/asound.state b/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state/mx8/asound.state new file mode 100644 index 0000000..3519e4b --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/alsa-state/alsa-state/mx8/asound.state @@ -0,0 +1,166 @@ +state.ucmimx8mmini { + control.1 { + iface MIXER + name 'Master Playback Volume' + value.0 101 + value.1 101 + comment { + access 'read write' + type INTEGER + count 2 + range '0 - 127' + dbmin -9999999 + dbmax 600 + dbvalue.0 -2000 + dbvalue.1 -2000 + } + } + control.2 { + iface MIXER + name 'Master Playback ZC Switch' + value.0 false + value.1 false + comment { + access 'read write' + type BOOLEAN + count 2 + } + } + control.3 { + iface MIXER + name 'Capture Volume' + value.0 31 + value.1 31 + comment { + access 'read write' + type INTEGER + count 2 + range '0 - 31' + dbmin -3450 + dbmax 1200 + dbvalue.0 1200 + dbvalue.1 1200 + } + } + control.4 { + iface MIXER + name 'Line Capture Switch' + value.0 false + value.1 false + comment { + access 'read write' + type BOOLEAN + count 2 + } + } + control.5 { + iface MIXER + name 'Mic Boost Volume' + value 0 + comment { + access 'read write' + type INTEGER + count 1 + range '0 - 1' + dbmin 0 + dbmax 2000 + dbvalue.0 0 + } + } + control.6 { + iface MIXER + name 'Mic Capture Switch' + value false + comment { + access 'read write' + type BOOLEAN + count 1 + } + } + control.7 { + iface MIXER + name 'Sidetone Playback Volume' + value 3 + comment { + access 'read write' + type INTEGER + count 1 + range '0 - 3' + dbmin -1500 + dbmax -600 + dbvalue.0 -600 + } + } + control.8 { + iface MIXER + name 'ADC High Pass Filter Switch' + value true + comment { + access 'read write' + type BOOLEAN + count 1 + } + } + control.9 { + iface MIXER + name 'Store DC Offset Switch' + value false + comment { + access 'read write' + type BOOLEAN + count 1 + } + } + control.10 { + iface MIXER + name 'Playback Deemphasis Switch' + value false + comment { + access 'read write' + type BOOLEAN + count 1 + } + } + control.11 { + iface MIXER + name 'Output Mixer Line Bypass Switch' + value false + comment { + access 'read write' + type BOOLEAN + count 1 + } + } + control.12 { + iface MIXER + name 'Output Mixer Mic Sidetone Switch' + value false + comment { + access 'read write' + type BOOLEAN + count 1 + } + } + control.13 { + iface MIXER + name 'Output Mixer HiFi Playback Switch' + value true + comment { + access 'read write' + type BOOLEAN + count 1 + } + } + control.14 { + iface MIXER + name 'Input Mux' + value 'Line In' + comment { + access 'read write' + type ENUMERATED + count 1 + item.0 'Line In' + item.1 Mic + } + } +} diff --git a/meta-bsp-imx8mm/recipes-bsp/bt-start/bt-start_%.bbappend b/meta-bsp-imx8mm/recipes-bsp/bt-start/bt-start_%.bbappend new file mode 100644 index 0000000..4afe6c4 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/bt-start/bt-start_%.bbappend @@ -0,0 +1,12 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/files:" + +SRC_URI_append = " \ + file://bt-start.mod \ +" + +do_install_append () { + + install -d ${D}${sbindir} + install -m 0755 ${WORKDIR}/bt-start.mod ${D}${sbindir}/bt-start + +} diff --git a/meta-bsp-imx8mm/recipes-bsp/bt-start/files/bt-start.mod b/meta-bsp-imx8mm/recipes-bsp/bt-start/files/bt-start.mod new file mode 100644 index 0000000..62ff79f --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/bt-start/files/bt-start.mod @@ -0,0 +1,30 @@ +#!/bin/bash + +### BEGIN INIT INFO +# Provides: bt-start +# Required-Start: $syslog +# Required-Stop: $syslog +# Default-Start: 2 3 4 5 +# Default-Stop: +# Short-Description: CompuLab bt-start +### END INIT INFO + +case "$1" in +start) + [[ -d /sys/class/bluetooth/hci0 ]] || hciattach -s 115200 /dev/ttymxc3 bcm43xx 1500000 flow + hciconfig hci0 up + ;; +stop) + hciconfig hci0 down + ;; +status) + hciconfig -a + ;; +*) +cat << eom + Usage: $0 {start|stop|status} +eom + exit 1 +esac + +exit 0 diff --git a/meta-bsp-imx8mm/recipes-bsp/firmware-imx/firmware-imx_%.bbappend b/meta-bsp-imx8mm/recipes-bsp/firmware-imx/firmware-imx_%.bbappend index ba9b96c..d783306 100644 --- a/meta-bsp-imx8mm/recipes-bsp/firmware-imx/firmware-imx_%.bbappend +++ b/meta-bsp-imx8mm/recipes-bsp/firmware-imx/firmware-imx_%.bbappend @@ -6,8 +6,8 @@ SRC_URI_append += " \ do_install_append () { cp -rfv ${WORKDIR}/lib/firmware/brcm ${D}${base_libdir}/firmware/ - echo cp -rfv ${WORKDIR}/lib/firmware/brcm ${D}${base_libdir}/firmware/ >/tmp/rep } FILES_${PN}-brcm += "${base_libdir}/firmware/brcm" +PACKAGES =+ "${PN}-brcm" COMPATIBLE_MACHINE = "(ucm-imx8m-mini)" diff --git a/meta-bsp-imx8mm/recipes-bsp/imx-atf/compulab/imx8mm.inc b/meta-bsp-imx8mm/recipes-bsp/imx-atf/compulab/imx8mm.inc new file mode 100644 index 0000000..fb91998 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/imx-atf/compulab/imx8mm.inc @@ -0,0 +1,3 @@ +SRC_URI_append_ucm-imx8m-mini = " \ + file://0001-imx8mm_bl31_setup-Unassign-DOM1-resources.patch \ +" diff --git a/meta-bsp-imx8mm/recipes-bsp/imx-atf/compulab/imx8mm/0001-imx8mm_bl31_setup-Unassign-DOM1-resources.patch b/meta-bsp-imx8mm/recipes-bsp/imx-atf/compulab/imx8mm/0001-imx8mm_bl31_setup-Unassign-DOM1-resources.patch new file mode 100644 index 0000000..6648f09 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/imx-atf/compulab/imx8mm/0001-imx8mm_bl31_setup-Unassign-DOM1-resources.patch @@ -0,0 +1,30 @@ +From 79aa3982e929a2fc5392036e39136310fc739854 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Thu, 2 May 2019 16:51:48 +0300 +Subject: [PATCH 1/1] imx8mm_bl31_setup: Unassign DOM1 resources + +Signed-off-by: Valentin Raevsky +--- + plat/imx/imx8mm/imx8mm_bl31_setup.c | 2 ++ + 1 file changed, 2 insertions(+) + +diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c +index aa1c336..b1beec0 100644 +--- a/plat/imx/imx8mm/imx8mm_bl31_setup.c ++++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c +@@ -308,10 +308,12 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + + bl31_tzc380_setup(); + ++#ifdef ASSIGN_M4_DOM1 + /* Assign M4 to domain 1 */ + mmio_write_32(IMX_RDC_BASE + 0x204, 0x1); + mmio_write_32(IMX_RDC_BASE + 0x518, 0xfc); + mmio_write_32(IMX_RDC_BASE + 0x5A4, 0xf3); ++#endif + + #if defined (CSU_RDC_TEST) + csu_test(); +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/imx-atf/imx-atf_2.0.bbappend b/meta-bsp-imx8mm/recipes-bsp/imx-atf/imx-atf_2.0.bbappend new file mode 100644 index 0000000..8de9225 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/imx-atf/imx-atf_2.0.bbappend @@ -0,0 +1,6 @@ +FILESEXTRAPATHS_prepend := "${THISDIR}/compulab/imx8mm:" + +include compulab/imx8mm.inc + +PACKAGE_ARCH = "${MACHINE_ARCH}" +COMPATIBLE_MACHINE = "(ucm-imx8m-mini)" diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm.inc b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm.inc index 6395ee8..c29d20a 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm.inc +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm.inc @@ -15,5 +15,16 @@ SRC_URI_append_ucm-imx8m-mini = " \ file://0013-ucm-imx8m-mini-release-U-Boot-v2018.03-ucm-imx8m-min.patch \ file://0014-ucm-imx8m-mini-config-Remove-unused-stuff.patch \ file://0015-ucm-imx8m-mini-Enable-uart4-for-bluetooth.patch \ + file://0016-ucm-imx8m-mini-ddr-Validate-new-setting.patch \ + file://0017-ucm-imx8m-mini-defconfig-Disable-CONFIG_NXP_TMU.patch \ + file://0018-ucm-imx8m-mini-config-Update-h-file.patch \ + file://0019-ucm-imx8m-mini-spl-Refacoring-ddr_init-call.patch \ + file://0020-ucm-imx8m-mini-Kconfig-Refacoring-ddr-init-config-op.patch \ + file://0021-ucm-imx8m-mini-Makefile-Refacoring-ddr-init-build-op.patch \ + file://0022-ucm-imx8m-mini-lpddr4_timing-Add-ucm-imx8m-mini-supp.patch \ + file://0023-ucm-imx8m-mini-config-Enable-the-new-LPDDR4-config.patch \ + file://0024-ucm-imx8m-mini-Move-FS-support-to-defconfig.patch \ + file://0025-ucm-imx8m-mini-config-CONFIG_IMX_OPTEE-y.patch \ + file://0026-set-extended-temperature-range.patch \ file://ucm-imx8m-mini_defconfig \ " diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0000-ucm-imx8m-mini-Add-basic-support.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0000-ucm-imx8m-mini-Add-basic-support.patch index 96396b5..5700d37 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0000-ucm-imx8m-mini-Add-basic-support.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0000-ucm-imx8m-mini-Add-basic-support.patch @@ -1,11 +1,11 @@ -From 6d3400ac2f2365d98f4be7edb154bb9a792d9ccc Mon Sep 17 00:00:00 2001 +From b219b5c84de317da38822d1c34cb6a3abf395927 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Thu, 7 Feb 2019 08:14:46 +0200 -Subject: [PATCH] ucm-imx8m-mini: Add basic support +Subject: [PATCH 00/25] ucm-imx8m-mini: Add basic support Signed-off-by: Valentin Raevsky --- - arch/arm/dts/Makefile | 265 +-- + arch/arm/dts/Makefile | 2 + arch/arm/dts/ucm-imx8m-mini.dts | 452 +++++ arch/arm/mach-imx/imx8m/Kconfig | 6 + board/compulab/common/Makefile | 1 + @@ -28,7 +28,7 @@ Signed-off-by: Valentin Raevsky board/compulab/ucm-imx8m-mini/ucm-imx8m-mini.c | 734 ++++++++ configs/ucm-imx8m-mini_defconfig | 56 + include/configs/ucm-imx8m-mini.h | 361 ++++ - 23 files changed, 6315 insertions(+), 209 deletions(-) + 23 files changed, 6259 insertions(+), 2 deletions(-) create mode 100644 arch/arm/dts/ucm-imx8m-mini.dts create mode 100644 board/compulab/common/mmc.c create mode 100644 board/compulab/common/pfuze.c @@ -50,494 +50,18 @@ Signed-off-by: Valentin Raevsky create mode 100644 include/configs/ucm-imx8m-mini.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile -index 845de59..9a7e056 100644 +index c841df0..126b4d3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -29,36 +29,18 @@ dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ - dtb-$(CONFIG_EXYNOS7420) += exynos7420-espresso7420.dtb - dtb-$(CONFIG_ARCH_ROCKCHIP) += \ - rk3036-sdk.dtb \ -- rk3128-evb.dtb \ -- rk3188-radxarock.dtb \ -- rk3288-evb.dtb \ -- rk3288-fennec.dtb \ - rk3288-firefly.dtb \ -- rk3288-miqi.dtb \ -- rk3288-phycore-rdk.dtb \ -- rk3288-popmetal.dtb \ -- rk3288-rock2-square.dtb \ -- rk3288-tinker.dtb \ - rk3288-veyron-jerry.dtb \ - rk3288-veyron-mickey.dtb \ - rk3288-veyron-minnie.dtb \ -- rk3288-vyasa.dtb \ -- rk3328-evb.dtb \ -- rk3368-lion.dtb \ -- rk3368-sheep.dtb \ -- rk3368-geekbox.dtb \ -- rk3368-px5-evb.dtb \ -- rk3399-evb.dtb \ -- rk3399-firefly.dtb \ -- rk3399-puma-ddr1333.dtb \ -- rk3399-puma-ddr1600.dtb \ -- rk3399-puma-ddr1866.dtb \ -- rv1108-evb.dtb -+ rk3288-rock2-square.dtb \ -+ rk3288-evb.dtb \ -+ rk3288-fennec.dtb \ -+ rk3288-tinker.dtb \ -+ rk3288-popmetal.dtb \ -+ rk3399-evb.dtb - dtb-$(CONFIG_ARCH_MESON) += \ -- meson-gxbb-odroidc2.dtb \ -- meson-gxl-s905x-p212.dtb \ -- meson-gxl-s905x-libretech-cc.dtb \ -- meson-gxl-s905x-khadas-vim.dtb -+ meson-gxbb-odroidc2.dtb - dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ - tegra20-medcom-wide.dtb \ - tegra20-paz00.dtb \ -@@ -67,6 +49,7 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ - tegra20-tec.dtb \ - tegra20-trimslice.dtb \ - tegra20-ventana.dtb \ -+ tegra20-whistler.dtb \ - tegra20-colibri.dtb \ - tegra30-apalis.dtb \ - tegra30-beaver.dtb \ -@@ -74,7 +57,6 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ - tegra30-colibri.dtb \ - tegra30-tec-ng.dtb \ - tegra114-dalmore.dtb \ -- tegra124-apalis.dtb \ - tegra124-jetson-tk1.dtb \ - tegra124-nyan-big.dtb \ - tegra124-cei-tk1-som.dtb \ -@@ -88,26 +70,20 @@ dtb-$(CONFIG_TEGRA) += tegra20-harmony.dtb \ - - dtb-$(CONFIG_ARCH_MVEBU) += \ - armada-3720-db.dtb \ -- armada-3720-espressobin.dtb \ - armada-375-db.dtb \ - armada-388-clearfog.dtb \ - armada-388-gp.dtb \ - armada-385-amc.dtb \ - armada-7040-db.dtb \ -- armada-7040-db-nand.dtb \ - armada-8040-db.dtb \ -- armada-8040-mcbin.dtb \ - armada-xp-gp.dtb \ - armada-xp-maxbcm.dtb \ - armada-xp-synology-ds414.dtb \ -- armada-xp-theadorable.dtb \ -- armada-38x-controlcenterdc.dtb -+ armada-xp-theadorable.dtb - - dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \ -- uniphier-ld11-global.dtb \ - uniphier-ld11-ref.dtb - dtb-$(CONFIG_ARCH_UNIPHIER_LD20) += \ -- uniphier-ld20-global.dtb \ - uniphier-ld20-ref.dtb - dtb-$(CONFIG_ARCH_UNIPHIER_LD4) += \ - uniphier-ld4-ref.dtb -@@ -124,34 +100,27 @@ dtb-$(CONFIG_ARCH_UNIPHIER_PXS2) += \ - uniphier-pxs2-vodka.dtb - dtb-$(CONFIG_ARCH_UNIPHIER_PXS3) += \ - uniphier-pxs3-ref.dtb -+dtb-$(CONFIG_ARCH_UNIPHIER_SLD3) += \ -+ uniphier-sld3-ref.dtb - dtb-$(CONFIG_ARCH_UNIPHIER_SLD8) += \ - uniphier-sld8-ref.dtb - --dtb-$(CONFIG_ARCH_ZYNQ) += \ -- zynq-cc108.dtb \ -- zynq-cse-qspi-single.dtb \ -+dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \ -+ zynq-zc706.dtb \ -+ zynq-zed.dtb \ -+ zynq-zybo.dtb \ - zynq-microzed.dtb \ - zynq-picozed.dtb \ -- zynq-syzygy-hub.dtb \ - zynq-topic-miami.dtb \ -- zynq-topic-miamilite.dtb \ - zynq-topic-miamiplus.dtb \ -- zynq-zc702.dtb \ -- zynq-zc706.dtb \ - zynq-zc770-xm010.dtb \ - zynq-zc770-xm011.dtb \ - zynq-zc770-xm012.dtb \ -- zynq-zc770-xm013.dtb \ -- zynq-zed.dtb \ -- zynq-zturn-myir.dtb \ -- zynq-zybo.dtb -+ zynq-zc770-xm013.dtb - dtb-$(CONFIG_ARCH_ZYNQMP) += \ - zynqmp-ep108.dtb \ -- zynqmp-mini-emmc.dtb \ -- zynqmp-mini-nand.dtb \ -- zynqmp-zcu102-revA.dtb \ -+ zynqmp-zcu102.dtb \ - zynqmp-zcu102-revB.dtb \ -- zynqmp-zcu102-rev1.0.dtb \ - zynqmp-zc1751-xm015-dc1.dtb \ - zynqmp-zc1751-xm016-dc2.dtb \ - zynqmp-zc1751-xm018-dc4.dtb \ -@@ -163,49 +132,38 @@ dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb am335x-bone.dtb \ - am335x-bonegreen.dtb \ - am335x-icev2.dtb \ - am335x-pxm50.dtb \ -- am335x-rut.dtb \ -- am335x-pdu001.dtb -+ am335x-rut.dtb - dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ - am43x-epos-evm.dtb \ - am437x-idk-evm.dtb --dtb-$(CONFIG_TI816X) += dm8168-evm.dtb - dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb - - dtb-$(CONFIG_ARCH_SOCFPGA) += \ -- socfpga_arria10_socdk_sdmmc.dtb \ - socfpga_arria5_socdk.dtb \ - socfpga_cyclone5_is1.dtb \ - socfpga_cyclone5_mcvevk.dtb \ - socfpga_cyclone5_socdk.dtb \ -- socfpga_cyclone5_dbm_soc1.dtb \ - socfpga_cyclone5_de0_nano_soc.dtb \ - socfpga_cyclone5_de1_soc.dtb \ -- socfpga_cyclone5_de10_nano.dtb \ - socfpga_cyclone5_sockit.dtb \ - socfpga_cyclone5_socrates.dtb \ - socfpga_cyclone5_sr1500.dtb \ - socfpga_cyclone5_vining_fpga.dtb - - dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \ -- dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb -+ dra72-evm-revc.dtb dra71-evm.dtb - dtb-$(CONFIG_TARGET_AM57XX_EVM) += am57xx-beagle-x15.dtb \ - am57xx-beagle-x15-revb1.dtb \ -- am57xx-beagle-x15-revc.dtb \ -- am574x-idk.dtb \ - am572x-idk.dtb \ - am571x-idk.dtb - dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb - --dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ -+dtb-$(CONFIG_LS102XA) += ls1021a-qds-duart.dtb \ - ls1021a-qds-lpuart.dtb \ - ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ - ls1021a-iot-duart.dtb - dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ -- fsl-ls2080a-rdb.dtb \ -- fsl-ls2081a-rdb.dtb \ -- fsl-ls2088a-rdb-qspi.dtb \ -- fsl-ls1088a-rdb.dtb \ -- fsl-ls1088a-qds.dtb -+ fsl-ls2080a-rdb.dtb - dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ - fsl-ls1043a-qds-lpuart.dtb \ - fsl-ls1043a-rdb.dtb \ -@@ -214,20 +172,11 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ - fsl-ls1046a-rdb.dtb \ - fsl-ls1012a-qds.dtb \ - fsl-ls1012a-rdb.dtb \ -- fsl-ls1012a-2g5rdb.dtb \ - fsl-ls1012a-frdm.dtb - --dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb --dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb -+dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb - --dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ -- stm32429i-eval.dtb \ -- stm32f469-disco.dtb -- --dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ -- stm32f769-disco.dtb --dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \ -- stm32h743i-eval.dtb -+dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb - - dtb-$(CONFIG_MACH_SUN4I) += \ - sun4i-a10-a1000.dtb \ -@@ -271,7 +220,6 @@ dtb-$(CONFIG_MACH_SUN5I) += \ - sun5i-a13-olinuxino-micro.dtb \ - sun5i-a13-q8-tablet.dtb \ - sun5i-a13-utoo-p66.dtb \ -- sun5i-gr8-chip-pro.dtb \ - sun5i-r8-chip.dtb - dtb-$(CONFIG_MACH_SUN6I) += \ - sun6i-a31-app4-evb1.dtb \ -@@ -329,18 +277,15 @@ dtb-$(CONFIG_MACH_SUN8I_A33) += \ - sun8i-a33-olinuxino.dtb \ - sun8i-a33-q8-tablet.dtb \ - sun8i-a33-sinlinx-sina33.dtb \ -- sun8i-r16-bananapi-m2m.dtb \ - sun8i-r16-nintendo-nes-classic-edition.dtb \ - sun8i-r16-parrot.dtb - dtb-$(CONFIG_MACH_SUN8I_A83T) += \ - sun8i-a83t-allwinner-h8homlet-v2.dtb \ -- sun8i-a83t-bananapi-m3.dtb \ - sun8i-a83t-cubietruck-plus.dtb \ -- sun8i-a83t-tbs-a711.dts -+ sun8i-a83t-sinovoip-bpi-m3.dtb - dtb-$(CONFIG_MACH_SUN8I_H3) += \ - sun8i-h2-plus-orangepi-zero.dtb \ - sun8i-h3-bananapi-m2-plus.dtb \ -- sun8i-h3-libretech-all-h3-cc.dtb \ - sun8i-h3-orangepi-2.dtb \ - sun8i-h3-orangepi-lite.dtb \ - sun8i-h3-orangepi-one.dtb \ -@@ -348,31 +293,13 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \ - sun8i-h3-orangepi-pc-plus.dtb \ - sun8i-h3-orangepi-plus.dtb \ - sun8i-h3-orangepi-plus2e.dtb \ -- sun8i-h3-nanopi-m1.dtb \ -- sun8i-h3-nanopi-m1-plus.dtb \ -- sun8i-h3-nanopi-neo.dtb \ -- sun8i-h3-nanopi-neo-air.dtb --dtb-$(CONFIG_MACH_SUN8I_R40) += \ -- sun8i-r40-bananapi-m2-ultra.dtb --dtb-$(CONFIG_MACH_SUN8I_V3S) += \ -- sun8i-v3s-licheepi-zero.dtb --dtb-$(CONFIG_MACH_SUN50I_H5) += \ -- sun50i-h5-nanopi-neo2.dtb \ -- sun50i-h5-nanopi-neo-plus2.dtb \ -- sun50i-h5-orangepi-pc2.dtb \ -- sun50i-h5-orangepi-prime.dtb \ -- sun50i-h5-orangepi-zero-plus2.dtb -+ sun8i-h3-nanopi-neo.dtb - dtb-$(CONFIG_MACH_SUN50I) += \ -- sun50i-a64-bananapi-m64.dtb \ -- sun50i-a64-nanopi-a64.dtb \ -- sun50i-a64-olinuxino.dtb \ -- sun50i-a64-orangepi-win.dtb \ - sun50i-a64-pine64-plus.dtb \ - sun50i-a64-pine64.dtb - dtb-$(CONFIG_MACH_SUN9I) += \ - sun9i-a80-optimus.dtb \ -- sun9i-a80-cubieboard4.dtb \ -- sun9i-a80-cx-a99.dtb -+ sun9i-a80-cubieboard4.dtb - - dtb-$(CONFIG_VF610) += vf500-colibri.dtb \ - vf610-colibri.dtb \ -@@ -389,27 +316,22 @@ dtb-$(CONFIG_MX6) += imx6ul-14x14-ddr3-arm2.dtb \ - imx6ul-14x14-evk.dtb \ - imx6ul-14x14-evk-emmc.dtb \ - imx6ul-14x14-evk-gpmi-weim.dtb \ -- imx6ul-9x9-evk.dtb \ - imx6ull-14x14-ddr3-arm2.dtb \ - imx6ull-14x14-ddr3-arm2-epdc.dtb \ - imx6ull-14x14-ddr3-arm2-emmc.dtb \ - imx6ull-14x14-ddr3-arm2-gpmi-weim.dtb \ - imx6ull-14x14-ddr3-arm2-tsc.dtb \ -- imx6ull-9x9-evk.dtb \ - imx6ull-14x14-evk.dtb \ - imx6ull-14x14-evk-emmc.dtb \ - imx6ull-14x14-evk-gpmi-weim.dtb \ -- imx6ulz-14x14-evk.dtb \ -- imx6ulz-14x14-evk-emmc.dtb \ -- imx6ulz-14x14-evk-gpmi-weim.dtb \ -- imx6sl-evk.dtb \ -- imx6sll-evk.dtb \ -+ imx6ul-9x9-evk.dtb \ -+ imx6ull-9x9-evk.dtb \ - imx6sll-lpddr2-arm2.dtb \ - imx6sll-lpddr3-arm2.dtb \ - imx6sll-lpddr3-arm2-ecspi.dtb \ -+ imx6sll-evk.dtb \ - imx6dl-arm2.dtb \ - imx6dl-icore.dtb \ -- imx6dl-icore-mipi.dtb \ - imx6dl-icore-rqs.dtb \ - imx6dl-sabreauto.dtb \ - imx6dl-sabreauto-ecspi.dtb \ -@@ -417,17 +339,15 @@ dtb-$(CONFIG_MX6) += imx6ul-14x14-ddr3-arm2.dtb \ - imx6dl-sabresd.dtb \ - imx6q-arm2.dtb \ - imx6q-pop-arm2.dtb \ -- imx6q-cm-fx6.dtb \ - imx6q-icore.dtb \ -- imx6q-icore-mipi.dtb \ - imx6q-icore-rqs.dtb \ -- imx6q-logicpd.dtb \ - imx6q-sabreauto.dtb \ - imx6q-sabreauto-ecspi.dtb \ - imx6q-sabreauto-gpmi-weim.dtb \ - imx6qp-sabreauto.dtb \ - imx6qp-sabreauto-ecspi.dtb \ - imx6qp-sabreauto-gpmi-weim.dtb \ -+ imx6sl-evk.dtb \ - imx6sx-14x14-arm2.dtb \ - imx6sx-17x17-arm2.dtb \ - imx6sx-17x17-arm2-ecspi.dtb \ -@@ -436,127 +356,60 @@ dtb-$(CONFIG_MX6) += imx6ul-14x14-ddr3-arm2.dtb \ - imx6sx-19x19-arm2-gpmi-weim.dtb \ - imx6sx-sabreauto.dtb \ - imx6sx-sdb.dtb \ -+ imx6sx-sdb-emmc.dtb \ -+ imx6q-sabresd.dtb \ -+ imx6qp-sabresd.dtb \ - imx6ul-geam-kit.dtb \ -- imx6ul-isiot-emmc.dtb \ -- imx6ul-isiot-nand.dtb \ -- imx6ul-opos6uldev.dtb -+ imx6dqscm-1gb-qwks-rev2-fix-ldo.dtb \ -+ imx6dqscm-1gb-qwks-rev3-fix-ldo.dtb \ -+ imx6dqscm-1gb-qwks-rev2-interleave-android-ldo.dtb \ -+ imx6dqscm-1gb-qwks-rev3-interleave-android-ldo.dtb \ -+ imx6sxscm-1gb-evb-ldo.dtb - - dtb-$(CONFIG_MX7) += imx7-colibri.dtb \ -- imx7d-sdb.dtb \ -- imx7d-sdb-epdc.dtb \ -- imx7d-sdb-gpmi-weim.dtb \ -- imx7d-sdb-qspi.dtb \ -- imx7d-sdb-reva.dtb \ -- imx7d-12x12-lpddr3-arm2.dtb \ -- imx7d-12x12-lpddr3-arm2-ecspi.dtb \ -- imx7d-12x12-lpddr3-arm2-qspi.dtb \ -- imx7d-12x12-ddr3-arm2.dtb \ -- imx7d-19x19-ddr3-arm2.dtb \ -- imx7d-19x19-lpddr2-arm2.dtb \ -- imx7d-19x19-lpddr3-arm2.dtb -+ imx7d-sdb.dtb \ -+ imx7d-sdb-epdc.dtb \ -+ imx7d-sdb-gpmi-weim.dtb \ -+ imx7d-sdb-qspi.dtb \ -+ imx7d-sdb-reva.dtb \ -+ imx7d-12x12-lpddr3-arm2.dtb \ -+ imx7d-12x12-lpddr3-arm2-ecspi.dtb \ -+ imx7d-12x12-lpddr3-arm2-qspi.dtb \ -+ imx7d-12x12-ddr3-arm2.dtb \ -+ imx7d-19x19-ddr3-arm2.dtb \ -+ imx7d-19x19-lpddr2-arm2.dtb \ -+ imx7d-19x19-lpddr3-arm2.dtb - - dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb \ -- imx7ulp-evk-emmc.dtb \ -- imx7ulp-evk-qspi.dtb \ -- imx7ulp-10x10-arm2.dtb \ -- imx7ulp-14x14-arm2.dtb -+ imx7ulp-evk-emmc.dtb \ -+ imx7ulp-evk-qspi.dtb \ -+ imx7ulp-10x10-arm2.dtb \ -+ imx7ulp-14x14-arm2.dtb - - dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \ - fsl-imx8mq-ddr3l-arm2.dtb \ -- fsl-imx8mq-ddr4-arm2.dtb \ - fsl-imx8mq-phanbell.dtb \ -- fsl-imx8mm-ddr3l-val.dtb \ -- fsl-imx8mm-ddr4-evk.dtb \ -+ fsl-imx8mq-ddr4-arm2.dtb \ - fsl-imx8mm-ddr4-val.dtb \ - fsl-imx8mm-evk.dtb - --dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8dx-ddr3-arm2.dtb \ -+dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qm-lpddr4-arm2.dtb \ - fsl-imx8qm-ddr4-arm2.dtb \ -- fsl-imx8qm-lpddr4-arm2.dtb \ - fsl-imx8qm-mek.dtb \ - fsl-imx8qm-mek-xen.dtb \ +@@ -479,6 +479,8 @@ dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8dx-17x17-val.dtb \ fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-mek.dtb --dtb-$(CONFIG_RCAR_GEN3) += \ -- r8a7795-h3ulcb.dtb \ -- r8a7795-salvator-x.dtb \ -- r8a7796-m3ulcb.dtb \ -- r8a7796-salvator-x.dtb \ -- r8a77965-salvator-x.dtb \ -- r8a77970-eagle.dtb \ -- r8a77995-draak.dtb +dtb-$(CONFIG_TARGET_UCM_IMX8M_MINI) += ucm-imx8m-mini.dtb - - dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ - keystone-k2l-evm.dtb \ - keystone-k2e-evm.dtb \ -- keystone-k2g-evm.dtb \ -- keystone-k2g-generic.dtb \ -- keystone-k2g-ice.dtb -- --dtb-$(CONFIG_TARGET_AT91SAM9261EK) += at91sam9261ek.dtb -- --dtb-$(CONFIG_TARGET_PM9263) += at91sam9263ek.dtb -- --dtb-$(CONFIG_TARGET_AT91SAM9263EK) += at91sam9263ek.dtb -- --dtb-$(CONFIG_TARGET_AT91SAM9RLEK) += at91sam9rlek.dtb -- --dtb-$(CONFIG_TARGET_AT91SAM9260EK) += \ -- at91sam9260ek.dtb \ -- at91sam9g20ek.dtb \ -- at91sam9g20ek_2mmc.dtb -- --dtb-$(CONFIG_TARGET_AT91SAM9M10G45EK) += at91sam9m10g45ek.dtb -- --dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \ -- at91sam9g15ek.dtb \ -- at91sam9g25ek.dtb \ -- at91sam9g35ek.dtb \ -- at91sam9x25ek.dtb \ -- at91sam9x35ek.dtb -- --dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb -- --dtb-$(CONFIG_TARGET_OMAP3_LOGIC) += \ -- logicpd-torpedo-37xx-devkit.dtb \ -- logicpd-som-lv-37xx-devkit.dtb -- --dtb-$(CONFIG_TARGET_OMAP3_EVM) += \ -- omap3-evm-37xx.dtb \ -- omap3-evm.dtb -- --dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \ -- omap3-beagle-xm-ab.dtb \ -- omap3-beagle-xm.dtb \ -- omap3-beagle.dtb -- --dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \ -- at91-sama5d2_ptc_ek.dtb -+ keystone-k2g-evm.dtb - - dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ - at91-sama5d2_xplained.dtb - --dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ -- at91-sama5d27_som1_ek.dtb -- --dtb-$(CONFIG_TARGET_SAMA5D3XEK) += \ -- sama5d31ek.dtb \ -- sama5d33ek.dtb \ -- sama5d34ek.dtb \ -- sama5d35ek.dtb \ -- sama5d36ek.dtb \ -- sama5d36ek_cmp.dtb -- --dtb-$(CONFIG_TARGET_SAMA5D3_XPLAINED) += \ -- at91-sama5d3_xplained.dtb -- --dtb-$(CONFIG_TARGET_SAMA5D4EK) += \ -- at91-sama5d4ek.dtb -- --dtb-$(CONFIG_TARGET_SAMA5D4_XPLAINED) += \ -- at91-sama5d4_xplained.dtb -- - dtb-$(CONFIG_ARCH_BCM283X) += \ - bcm2835-rpi-a-plus.dtb \ - bcm2835-rpi-a.dtb \ -@@ -568,8 +421,6 @@ dtb-$(CONFIG_ARCH_BCM283X) += \ - - dtb-$(CONFIG_ARCH_ASPEED) += ast2500-evb.dtb - --dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb -- - targets += $(dtb-y) - - # Add any required device tree compiler flags here ++ + dtb-$(CONFIG_RCAR_GEN3) += \ + r8a7795-h3ulcb.dtb \ + r8a7795-salvator-x.dtb \ diff --git a/arch/arm/dts/ucm-imx8m-mini.dts b/arch/arm/dts/ucm-imx8m-mini.dts new file mode 100644 index 0000000..112345b @@ -997,10 +521,10 @@ index 0000000..112345b + status = "disabled"; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig -index 249436c..ccff991 100644 +index 09779cd..27c020f 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig -@@ -60,6 +60,11 @@ config TARGET_IMX8MM_DDR4_EVK +@@ -66,6 +66,11 @@ config TARGET_IMX8MM_DDR4_EVK select SUPPORT_SPL select IMX8M_DDR4 @@ -1012,8 +536,8 @@ index 249436c..ccff991 100644 endchoice config SYS_SOC -@@ -70,5 +75,6 @@ source "board/freescale/imx8mq_arm2/Kconfig" - source "board/freescale/imx8mq_phanbell/Kconfig" +@@ -77,5 +82,6 @@ source "board/freescale/imx8mq_phanbell/Kconfig" + source "board/freescale/imx8mq_aiy/Kconfig" source "board/freescale/imx8mm_evk/Kconfig" source "board/freescale/imx8mm_val/Kconfig" +source "board/compulab/ucm-imx8m-mini/Kconfig" @@ -2012,1315 +1536,1315 @@ index 0000000..252b11e +#endif diff --git a/board/compulab/ucm-imx8m-mini/ddr/ddr_init.c b/board/compulab/ucm-imx8m-mini/ddr/ddr_init.c new file mode 100644 -index 0000000..d3e84da +index 0000000..6093d1b --- /dev/null +++ b/board/compulab/ucm-imx8m-mini/ddr/ddr_init.c @@ -0,0 +1,255 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ * -+ * Generated code from MX8M_DDR_tool -+ * Align with uboot-imx_v2017.03_4.9.51_imx8m_ga -+ */ -+ -+#include -+#include -+#include -+#include -+#include -+#include -+#include "ddr.h" -+ -+#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG -+#define ddr_printf(args...) printf(args) -+#else -+#define ddr_printf(args...) -+#endif -+ -+#include "wait_ddrphy_training_complete.c" -+#ifndef SRC_DDRC_RCR_ADDR -+#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000 -+#endif -+#ifndef DDR_CSD1_BASE_ADDR -+#define DDR_CSD1_BASE_ADDR 0x40000000 -+#endif -+#define SILICON_TRAIN -+ -+void ddr_cfg_phy(void); -+volatile unsigned int tmp, tmp_t, i; -+void ddr_init(void) -+{ -+ /** Initialize DDR clock and DDRC registers **/ -+ reg32_write(0x30391000,0x8f00003f); -+ reg32_write(0x30391000,0x8f00000f); -+ reg32_write(0x3038a088,0x7070000); -+ reg32_write(0x3038a084,0x4030000); -+ reg32_write(0x303a00ec,0xffff); -+ tmp=reg32_read(0x303a00f8); -+ tmp |= 0x20; -+ reg32_write(0x303a00f8,tmp); -+ reg32_write(0x30391004,0x8f000000); -+ reg32_write(0x30360054,0xfa080); -+ reg32_write(0x30360058,0x0); -+ tmp=reg32_read(0x30360050); -+ tmp |= 0x200; -+ reg32_write(0x30360050,tmp); -+ tmp=reg32_read(0x30360050); -+ tmp &= ~0x10; -+ reg32_write(0x30360050,tmp); -+ do{ -+ tmp=reg32_read(0x30360050); -+ if(tmp&0x80000000) break; -+ }while(1); -+ reg32_write(0x30391000,0x8f000006); -+ reg32_write(0x3d400304,0x1); -+ reg32_write(0x3d400030,0x1); -+ reg32_write(0x3d400000,0xa3080020); -+ reg32_write(0x3d400020,0x223); -+ reg32_write(0x3d400024,0x16e3600); -+ reg32_write(0x3d400064,0x5b00d2); -+ reg32_write(0x3d4000d0,0xc00305ba); -+ reg32_write(0x3d4000d4,0x940000); -+ reg32_write(0x3d4000dc,0xd4002d); -+ reg32_write(0x3d4000e0,0x310008); -+ reg32_write(0x3d4000e8,0x66004d); -+ reg32_write(0x3d4000ec,0x16004d); -+ reg32_write(0x3d400100,0x191e1920); -+ reg32_write(0x3d400104,0x60630); -+ reg32_write(0x3d40010c,0xb0b000); -+ reg32_write(0x3d400110,0xe04080e); -+ reg32_write(0x3d400114,0x2040c0c); -+ reg32_write(0x3d400118,0x1010007); -+ reg32_write(0x3d40011c,0x401); -+ reg32_write(0x3d400130,0x20600); -+ reg32_write(0x3d400134,0xc100002); -+ reg32_write(0x3d400138,0xd8); -+ reg32_write(0x3d400144,0x96004b); -+ reg32_write(0x3d400180,0x2ee0017); -+ reg32_write(0x3d400184,0x2605b8e); -+ reg32_write(0x3d400188,0x0); -+ reg32_write(0x3d400190,0x497820a); -+ reg32_write(0x3d400194,0x80303); -+ reg32_write(0x3d4001b4,0x170a); -+ reg32_write(0x3d4001a0,0xe0400018); -+ reg32_write(0x3d4001a4,0xdf00e4); -+ reg32_write(0x3d4001a8,0x80000000); -+ reg32_write(0x3d4001b0,0x11); -+ reg32_write(0x3d4001c0,0x1); -+ reg32_write(0x3d4001c4,0x0); -+ reg32_write(0x3d4000f4,0x639); -+ reg32_write(0x3d400108,0x70e1213); -+ reg32_write(0x3d400200,0x16); -+ reg32_write(0x3d40020c,0x0); -+ reg32_write(0x3d400210,0x1f1f); -+ reg32_write(0x3d400204,0x80808); -+ reg32_write(0x3d400214,0x7070707); -+ reg32_write(0x3d400218,0xf070707); -+ reg32_write(0x3d400250,0x29001701); -+ reg32_write(0x3d400254,0x2c); -+ reg32_write(0x3d40025c,0x4000030); -+ reg32_write(0x3d400264,0x900093e7); -+ reg32_write(0x3d40026c,0x2005574); -+ reg32_write(0x3d400400,0x111); -+ reg32_write(0x3d400408,0x72ff); -+ reg32_write(0x3d400494,0x2100e07); -+ reg32_write(0x3d400498,0x620096); -+ reg32_write(0x3d40049c,0x1100e07); -+ reg32_write(0x3d4004a0,0xc8012c); -+ reg32_write(0x3d402020,0x21); -+ reg32_write(0x3d402024,0x30d400); -+ reg32_write(0x3d402050,0x20d040); -+ reg32_write(0x3d402064,0xc001c); -+ reg32_write(0x3d4020dc,0x840000); -+ reg32_write(0x3d4020e0,0x310008); -+ reg32_write(0x3d4020e8,0x66004d); -+ reg32_write(0x3d4020ec,0x16004d); -+ reg32_write(0x3d402100,0xa040305); -+ reg32_write(0x3d402104,0x30407); -+ reg32_write(0x3d402108,0x203060b); -+ reg32_write(0x3d40210c,0x505000); -+ reg32_write(0x3d402110,0x2040202); -+ reg32_write(0x3d402114,0x2030202); -+ reg32_write(0x3d402118,0x1010004); -+ reg32_write(0x3d40211c,0x301); -+ reg32_write(0x3d402130,0x20300); -+ reg32_write(0x3d402134,0xa100002); -+ reg32_write(0x3d402138,0x1d); -+ reg32_write(0x3d402144,0x14000a); -+ reg32_write(0x3d402180,0x640004); -+ reg32_write(0x3d402190,0x3818200); -+ reg32_write(0x3d402194,0x80303); -+ reg32_write(0x3d4021b4,0x100); -+ reg32_write(0x3d403020,0x21); -+ reg32_write(0x3d403024,0xc3500); -+ reg32_write(0x3d403050,0x20d040); -+ reg32_write(0x3d403064,0x30007); -+ reg32_write(0x3d4030dc,0x840000); -+ reg32_write(0x3d4030e0,0x310008); -+ reg32_write(0x3d4030e8,0x66004d); -+ reg32_write(0x3d4030ec,0x16004d); -+ reg32_write(0x3d403100,0xa010102); -+ reg32_write(0x3d403104,0x30404); -+ reg32_write(0x3d403108,0x203060b); -+ reg32_write(0x3d40310c,0x505000); -+ reg32_write(0x3d403110,0x2040202); -+ reg32_write(0x3d403114,0x2030202); -+ reg32_write(0x3d403118,0x1010004); -+ reg32_write(0x3d40311c,0x301); -+ reg32_write(0x3d403130,0x20300); -+ reg32_write(0x3d403134,0xa100002); -+ reg32_write(0x3d403138,0x8); -+ reg32_write(0x3d403144,0x50003); -+ reg32_write(0x3d403180,0x190004); -+ reg32_write(0x3d403190,0x3818200); -+ reg32_write(0x3d403194,0x80303); -+ reg32_write(0x3d4031b4,0x100); -+ reg32_write(0x3d400028,0x0); -+ reg32_write(0x30391000,0x8f000004); -+ reg32_write(0x30391000,0x8f000000); -+ reg32_write(0x3d400304,0x0); -+ reg32_write(0x3d400030,0xa8); -+ reg32_write(0x3d400320,0x0); -+ reg32_write(0x3d000000,0x1); -+ reg32_write(0x3d4001b0,0x10); -+ reg32_write(0x3c040280,0x0); -+ reg32_write(0x3c040284,0x1); -+ reg32_write(0x3c040288,0x2); -+ reg32_write(0x3c04028c,0x3); -+ reg32_write(0x3c040290,0x4); -+ reg32_write(0x3c040294,0x5); -+ reg32_write(0x3c040298,0x6); -+ reg32_write(0x3c04029c,0x7); -+ reg32_write(0x3c044280,0x0); -+ reg32_write(0x3c044284,0x1); -+ reg32_write(0x3c044288,0x3); -+ reg32_write(0x3c04428c,0x4); -+ reg32_write(0x3c044290,0x5); -+ reg32_write(0x3c044294,0x2); -+ reg32_write(0x3c044298,0x7); -+ reg32_write(0x3c04429c,0x6); -+ reg32_write(0x3c048280,0x0); -+ reg32_write(0x3c048284,0x1); -+ reg32_write(0x3c048288,0x3); -+ reg32_write(0x3c04828c,0x2); -+ reg32_write(0x3c048290,0x5); -+ reg32_write(0x3c048294,0x4); -+ reg32_write(0x3c048298,0x7); -+ reg32_write(0x3c04829c,0x6); -+ reg32_write(0x3c04c280,0x0); -+ reg32_write(0x3c04c284,0x1); -+ reg32_write(0x3c04c288,0x2); -+ reg32_write(0x3c04c28c,0x3); -+ reg32_write(0x3c04c290,0x4); -+ reg32_write(0x3c04c294,0x5); -+ reg32_write(0x3c04c298,0x6); -+ reg32_write(0x3c04c29c,0x7); -+ -+ /* Configure DDR PHY's registers */ -+ ddr_cfg_phy(); -+ -+ reg32_write(DDRC_RFSHCTL3(0), 0x00000000); -+ reg32_write(DDRC_SWCTL(0), 0x0000); -+ /* -+ * ------------------- 9 ------------------- -+ * Set DFIMISC.dfi_init_start to 1 -+ * ----------------------------------------- -+ */ -+ reg32_write(DDRC_DFIMISC(0), 0x00000030); -+ reg32_write(DDRC_SWCTL(0), 0x0001); -+ -+ /* wait DFISTAT.dfi_init_complete to 1 */ -+ tmp_t = 0; -+ while(tmp_t==0){ -+ tmp = reg32_read(DDRC_DFISTAT(0)); -+ tmp_t = tmp & 0x01; -+ tmp = reg32_read(DDRC_MRSTAT(0)); -+ } -+ -+ reg32_write(DDRC_SWCTL(0), 0x0000); -+ -+ /* clear DFIMISC.dfi_init_complete_en */ -+ reg32_write(DDRC_DFIMISC(0), 0x00000010); -+ reg32_write(DDRC_DFIMISC(0), 0x00000011); -+ reg32_write(DDRC_PWRCTL(0), 0x00000088); -+ -+ tmp = reg32_read(DDRC_CRCPARSTAT(0)); -+ /* -+ * set SWCTL.sw_done to enable quasi-dynamic register -+ * programming outside reset. -+ */ -+ reg32_write(DDRC_SWCTL(0), 0x00000001); -+ -+ /* wait SWSTAT.sw_done_ack to 1 */ -+ while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0) -+ ; -+ -+ /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ -+ while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1) -+ ; -+ -+ reg32_write(DDRC_PWRCTL(0), 0x00000088); -+ /* reg32_write(DDRC_PWRCTL(0), 0x018a); */ -+ tmp = reg32_read(DDRC_CRCPARSTAT(0)); -+ -+ /* enable port 0 */ -+ reg32_write(DDRC_PCTRL_0(0), 0x00000001); -+ /* enable DDR auto-refresh mode */ -+ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; -+ reg32_write(DDRC_RFSHCTL3(0), tmp); -+} ++/* ++ * Copyright 2017 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ * ++ * Generated code from MX8M_DDR_tool ++ * Align with uboot-imx_v2017.03_4.9.51_imx8m_ga ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++#include "ddr.h" ++ ++#ifdef CONFIG_ENABLE_DDR_TRAINING_DEBUG ++#define ddr_printf(args...) printf(args) ++#else ++#define ddr_printf(args...) ++#endif ++ ++#include "wait_ddrphy_training_complete.c" ++#ifndef SRC_DDRC_RCR_ADDR ++#define SRC_DDRC_RCR_ADDR SRC_IPS_BASE_ADDR +0x1000 ++#endif ++#ifndef DDR_CSD1_BASE_ADDR ++#define DDR_CSD1_BASE_ADDR 0x40000000 ++#endif ++#define SILICON_TRAIN ++ ++void ddr_cfg_phy(void); ++volatile unsigned int tmp, tmp_t, i; ++void ddr_init(void) ++{ ++ /** Initialize DDR clock and DDRC registers **/ ++ reg32_write(0x30391000,0x8f00003f); ++ reg32_write(0x30391000,0x8f00000f); ++ reg32_write(0x3038a088,0x7070000); ++ reg32_write(0x3038a084,0x4030000); ++ reg32_write(0x303a00ec,0xffff); ++ tmp=reg32_read(0x303a00f8); ++ tmp |= 0x20; ++ reg32_write(0x303a00f8,tmp); ++ reg32_write(0x30391004,0x8f000000); ++ reg32_write(0x30360054,0xfa080); ++ reg32_write(0x30360058,0x0); ++ tmp=reg32_read(0x30360050); ++ tmp |= 0x200; ++ reg32_write(0x30360050,tmp); ++ tmp=reg32_read(0x30360050); ++ tmp &= ~0x10; ++ reg32_write(0x30360050,tmp); ++ do{ ++ tmp=reg32_read(0x30360050); ++ if(tmp&0x80000000) break; ++ }while(1); ++ reg32_write(0x30391000,0x8f000006); ++ reg32_write(0x3d400304,0x1); ++ reg32_write(0x3d400030,0x1); ++ reg32_write(0x3d400000,0xa3080020); ++ reg32_write(0x3d400020,0x223); ++ reg32_write(0x3d400024,0x16e3600); ++ reg32_write(0x3d400064,0x5b00d2); ++ reg32_write(0x3d4000d0,0xc00305ba); ++ reg32_write(0x3d4000d4,0x940000); ++ reg32_write(0x3d4000dc,0xd4002d); ++ reg32_write(0x3d4000e0,0x310008); ++ reg32_write(0x3d4000e8,0x66004d); ++ reg32_write(0x3d4000ec,0x16004d); ++ reg32_write(0x3d400100,0x191e1920); ++ reg32_write(0x3d400104,0x60630); ++ reg32_write(0x3d40010c,0xb0b000); ++ reg32_write(0x3d400110,0xe04080e); ++ reg32_write(0x3d400114,0x2040c0c); ++ reg32_write(0x3d400118,0x1010007); ++ reg32_write(0x3d40011c,0x401); ++ reg32_write(0x3d400130,0x20600); ++ reg32_write(0x3d400134,0xc100002); ++ reg32_write(0x3d400138,0xd8); ++ reg32_write(0x3d400144,0x96004b); ++ reg32_write(0x3d400180,0x2ee0017); ++ reg32_write(0x3d400184,0x2605b8e); ++ reg32_write(0x3d400188,0x0); ++ reg32_write(0x3d400190,0x497820a); ++ reg32_write(0x3d400194,0x80303); ++ reg32_write(0x3d4001b4,0x170a); ++ reg32_write(0x3d4001a0,0xe0400018); ++ reg32_write(0x3d4001a4,0xdf00e4); ++ reg32_write(0x3d4001a8,0x80000000); ++ reg32_write(0x3d4001b0,0x11); ++ reg32_write(0x3d4001c0,0x1); ++ reg32_write(0x3d4001c4,0x0); ++ reg32_write(0x3d4000f4,0x639); ++ reg32_write(0x3d400108,0x70e1213); ++ reg32_write(0x3d400200,0x16); ++ reg32_write(0x3d40020c,0x0); ++ reg32_write(0x3d400210,0x1f1f); ++ reg32_write(0x3d400204,0x80808); ++ reg32_write(0x3d400214,0x7070707); ++ reg32_write(0x3d400218,0xf070707); ++ reg32_write(0x3d400250,0x29001701); ++ reg32_write(0x3d400254,0x2c); ++ reg32_write(0x3d40025c,0x4000030); ++ reg32_write(0x3d400264,0x900093e7); ++ reg32_write(0x3d40026c,0x2005574); ++ reg32_write(0x3d400400,0x111); ++ reg32_write(0x3d400408,0x72ff); ++ reg32_write(0x3d400494,0x2100e07); ++ reg32_write(0x3d400498,0x620096); ++ reg32_write(0x3d40049c,0x1100e07); ++ reg32_write(0x3d4004a0,0xc8012c); ++ reg32_write(0x3d402020,0x21); ++ reg32_write(0x3d402024,0x30d400); ++ reg32_write(0x3d402050,0x20d040); ++ reg32_write(0x3d402064,0xc001c); ++ reg32_write(0x3d4020dc,0x840000); ++ reg32_write(0x3d4020e0,0x310008); ++ reg32_write(0x3d4020e8,0x66004d); ++ reg32_write(0x3d4020ec,0x16004d); ++ reg32_write(0x3d402100,0xa040305); ++ reg32_write(0x3d402104,0x30407); ++ reg32_write(0x3d402108,0x203060b); ++ reg32_write(0x3d40210c,0x505000); ++ reg32_write(0x3d402110,0x2040202); ++ reg32_write(0x3d402114,0x2030202); ++ reg32_write(0x3d402118,0x1010004); ++ reg32_write(0x3d40211c,0x301); ++ reg32_write(0x3d402130,0x20300); ++ reg32_write(0x3d402134,0xa100002); ++ reg32_write(0x3d402138,0x1d); ++ reg32_write(0x3d402144,0x14000a); ++ reg32_write(0x3d402180,0x640004); ++ reg32_write(0x3d402190,0x3818200); ++ reg32_write(0x3d402194,0x80303); ++ reg32_write(0x3d4021b4,0x100); ++ reg32_write(0x3d403020,0x21); ++ reg32_write(0x3d403024,0xc3500); ++ reg32_write(0x3d403050,0x20d040); ++ reg32_write(0x3d403064,0x30007); ++ reg32_write(0x3d4030dc,0x840000); ++ reg32_write(0x3d4030e0,0x310008); ++ reg32_write(0x3d4030e8,0x66004d); ++ reg32_write(0x3d4030ec,0x16004d); ++ reg32_write(0x3d403100,0xa010102); ++ reg32_write(0x3d403104,0x30404); ++ reg32_write(0x3d403108,0x203060b); ++ reg32_write(0x3d40310c,0x505000); ++ reg32_write(0x3d403110,0x2040202); ++ reg32_write(0x3d403114,0x2030202); ++ reg32_write(0x3d403118,0x1010004); ++ reg32_write(0x3d40311c,0x301); ++ reg32_write(0x3d403130,0x20300); ++ reg32_write(0x3d403134,0xa100002); ++ reg32_write(0x3d403138,0x8); ++ reg32_write(0x3d403144,0x50003); ++ reg32_write(0x3d403180,0x190004); ++ reg32_write(0x3d403190,0x3818200); ++ reg32_write(0x3d403194,0x80303); ++ reg32_write(0x3d4031b4,0x100); ++ reg32_write(0x3d400028,0x0); ++ reg32_write(0x30391000,0x8f000004); ++ reg32_write(0x30391000,0x8f000000); ++ reg32_write(0x3d400304,0x0); ++ reg32_write(0x3d400030,0xa8); ++ reg32_write(0x3d400320,0x0); ++ reg32_write(0x3d000000,0x1); ++ reg32_write(0x3d4001b0,0x10); ++ reg32_write(0x3c040280,0x0); ++ reg32_write(0x3c040284,0x1); ++ reg32_write(0x3c040288,0x2); ++ reg32_write(0x3c04028c,0x3); ++ reg32_write(0x3c040290,0x4); ++ reg32_write(0x3c040294,0x5); ++ reg32_write(0x3c040298,0x6); ++ reg32_write(0x3c04029c,0x7); ++ reg32_write(0x3c044280,0x0); ++ reg32_write(0x3c044284,0x1); ++ reg32_write(0x3c044288,0x3); ++ reg32_write(0x3c04428c,0x4); ++ reg32_write(0x3c044290,0x5); ++ reg32_write(0x3c044294,0x2); ++ reg32_write(0x3c044298,0x7); ++ reg32_write(0x3c04429c,0x6); ++ reg32_write(0x3c048280,0x0); ++ reg32_write(0x3c048284,0x1); ++ reg32_write(0x3c048288,0x3); ++ reg32_write(0x3c04828c,0x2); ++ reg32_write(0x3c048290,0x5); ++ reg32_write(0x3c048294,0x4); ++ reg32_write(0x3c048298,0x7); ++ reg32_write(0x3c04829c,0x6); ++ reg32_write(0x3c04c280,0x0); ++ reg32_write(0x3c04c284,0x1); ++ reg32_write(0x3c04c288,0x2); ++ reg32_write(0x3c04c28c,0x3); ++ reg32_write(0x3c04c290,0x4); ++ reg32_write(0x3c04c294,0x5); ++ reg32_write(0x3c04c298,0x6); ++ reg32_write(0x3c04c29c,0x7); ++ ++ /* Configure DDR PHY's registers */ ++ ddr_cfg_phy(); ++ ++ reg32_write(DDRC_RFSHCTL3(0), 0x00000000); ++ reg32_write(DDRC_SWCTL(0), 0x0000); ++ /* ++ * ------------------- 9 ------------------- ++ * Set DFIMISC.dfi_init_start to 1 ++ * ----------------------------------------- ++ */ ++ reg32_write(DDRC_DFIMISC(0), 0x00000030); ++ reg32_write(DDRC_SWCTL(0), 0x0001); ++ ++ /* wait DFISTAT.dfi_init_complete to 1 */ ++ tmp_t = 0; ++ while(tmp_t==0){ ++ tmp = reg32_read(DDRC_DFISTAT(0)); ++ tmp_t = tmp & 0x01; ++ tmp = reg32_read(DDRC_MRSTAT(0)); ++ } ++ ++ reg32_write(DDRC_SWCTL(0), 0x0000); ++ ++ /* clear DFIMISC.dfi_init_complete_en */ ++ reg32_write(DDRC_DFIMISC(0), 0x00000010); ++ reg32_write(DDRC_DFIMISC(0), 0x00000011); ++ reg32_write(DDRC_PWRCTL(0), 0x00000088); ++ ++ tmp = reg32_read(DDRC_CRCPARSTAT(0)); ++ /* ++ * set SWCTL.sw_done to enable quasi-dynamic register ++ * programming outside reset. ++ */ ++ reg32_write(DDRC_SWCTL(0), 0x00000001); ++ ++ /* wait SWSTAT.sw_done_ack to 1 */ ++ while((reg32_read(DDRC_SWSTAT(0)) & 0x1) == 0) ++ ; ++ ++ /* wait STAT.operating_mode([1:0] for ddr3) to normal state */ ++ while ((reg32_read(DDRC_STAT(0)) & 0x3) != 0x1) ++ ; ++ ++ reg32_write(DDRC_PWRCTL(0), 0x00000088); ++ /* reg32_write(DDRC_PWRCTL(0), 0x018a); */ ++ tmp = reg32_read(DDRC_CRCPARSTAT(0)); ++ ++ /* enable port 0 */ ++ reg32_write(DDRC_PCTRL_0(0), 0x00000001); ++ /* enable DDR auto-refresh mode */ ++ tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; ++ reg32_write(DDRC_RFSHCTL3(0), tmp); ++} diff --git a/board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c b/board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c new file mode 100644 -index 0000000..019aae5 +index 0000000..8116069 --- /dev/null +++ b/board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c @@ -0,0 +1,1044 @@ -+/* -+ * Copyright 2017 NXP -+ * -+ * SPDX-License-Identifier: GPL-2.0+ -+ * -+ * Generated code from MX8M_DDR_tool -+ * Align with uboot-imx_v2017.03_4.9.51_imx8m_ga -+ */ -+ -+#include -+#include -+#include -+#include -+#include "ddr.h" -+ -+extern void wait_ddrphy_training_complete(void); -+void ddr_cfg_phy(void) { -+ unsigned int tmp, tmp_t; -+ -+ //Init DDRPHY register... -+ reg32_write(0x3c04017c,0x1ff); -+ reg32_write(0x3c04057c,0x1ff); -+ reg32_write(0x3c04417c,0x1ff); -+ reg32_write(0x3c04457c,0x1ff); -+ reg32_write(0x3c04817c,0x1ff); -+ reg32_write(0x3c04857c,0x1ff); -+ reg32_write(0x3c04c17c,0x1ff); -+ reg32_write(0x3c04c57c,0x1ff); -+ reg32_write(0x3c44017c,0x1ff); -+ reg32_write(0x3c44057c,0x1ff); -+ reg32_write(0x3c44417c,0x1ff); -+ reg32_write(0x3c44457c,0x1ff); -+ reg32_write(0x3c44817c,0x1ff); -+ reg32_write(0x3c44857c,0x1ff); -+ reg32_write(0x3c44c17c,0x1ff); -+ reg32_write(0x3c44c57c,0x1ff); -+ reg32_write(0x3c84017c,0x1ff); -+ reg32_write(0x3c84057c,0x1ff); -+ reg32_write(0x3c84417c,0x1ff); -+ reg32_write(0x3c84457c,0x1ff); -+ reg32_write(0x3c84817c,0x1ff); -+ reg32_write(0x3c84857c,0x1ff); -+ reg32_write(0x3c84c17c,0x1ff); -+ reg32_write(0x3c84c57c,0x1ff); -+ reg32_write(0x3c000154,0x1ff); -+ reg32_write(0x3c004154,0x1ff); -+ reg32_write(0x3c008154,0x1ff); -+ reg32_write(0x3c00c154,0x1ff); -+ reg32_write(0x3c010154,0x1ff); -+ reg32_write(0x3c014154,0x1ff); -+ reg32_write(0x3c018154,0x1ff); -+ reg32_write(0x3c01c154,0x1ff); -+ reg32_write(0x3c020154,0x1ff); -+ reg32_write(0x3c024154,0x1ff); -+ reg32_write(0x3c080314,0x19); -+ reg32_write(0x3c480314,0x7); -+ reg32_write(0x3c880314,0x7); -+ reg32_write(0x3c0800b8,0x2); -+ reg32_write(0x3c4800b8,0x2); -+ reg32_write(0x3c8800b8,0x2); -+ reg32_write(0x3c240810,0x0); -+ reg32_write(0x3c640810,0x0); -+ reg32_write(0x3ca40810,0x0); -+ reg32_write(0x3c080090,0xab); -+ reg32_write(0x3c0800e8,0x0); -+ reg32_write(0x3c480090,0xab); -+ reg32_write(0x3c0800e8,0x0); -+ reg32_write(0x3c880090,0xab); -+ reg32_write(0x3c0800e8,0x0); -+ reg32_write(0x3c080158,0x3); -+ reg32_write(0x3c480158,0xa); -+ reg32_write(0x3c880158,0xa); -+ reg32_write(0x3c040134,0xe00); -+ reg32_write(0x3c040534,0xe00); -+ reg32_write(0x3c044134,0xe00); -+ reg32_write(0x3c044534,0xe00); -+ reg32_write(0x3c048134,0xe00); -+ reg32_write(0x3c048534,0xe00); -+ reg32_write(0x3c04c134,0xe00); -+ reg32_write(0x3c04c534,0xe00); -+ reg32_write(0x3c440134,0xe00); -+ reg32_write(0x3c440534,0xe00); -+ reg32_write(0x3c444134,0xe00); -+ reg32_write(0x3c444534,0xe00); -+ reg32_write(0x3c448134,0xe00); -+ reg32_write(0x3c448534,0xe00); -+ reg32_write(0x3c44c134,0xe00); -+ reg32_write(0x3c44c534,0xe00); -+ reg32_write(0x3c840134,0xe00); -+ reg32_write(0x3c840534,0xe00); -+ reg32_write(0x3c844134,0xe00); -+ reg32_write(0x3c844534,0xe00); -+ reg32_write(0x3c848134,0xe00); -+ reg32_write(0x3c848534,0xe00); -+ reg32_write(0x3c84c134,0xe00); -+ reg32_write(0x3c84c534,0xe00); -+ reg32_write(0x3c040124,0xfbe); -+ reg32_write(0x3c040524,0xfbe); -+ reg32_write(0x3c044124,0xfbe); -+ reg32_write(0x3c044524,0xfbe); -+ reg32_write(0x3c048124,0xfbe); -+ reg32_write(0x3c048524,0xfbe); -+ reg32_write(0x3c04c124,0xfbe); -+ reg32_write(0x3c04c524,0xfbe); -+ reg32_write(0x3c440124,0xfbe); -+ reg32_write(0x3c440524,0xfbe); -+ reg32_write(0x3c444124,0xfbe); -+ reg32_write(0x3c444524,0xfbe); -+ reg32_write(0x3c448124,0xfbe); -+ reg32_write(0x3c448524,0xfbe); -+ reg32_write(0x3c44c124,0xfbe); -+ reg32_write(0x3c44c524,0xfbe); -+ reg32_write(0x3c840124,0xfbe); -+ reg32_write(0x3c840524,0xfbe); -+ reg32_write(0x3c844124,0xfbe); -+ reg32_write(0x3c844524,0xfbe); -+ reg32_write(0x3c848124,0xfbe); -+ reg32_write(0x3c848524,0xfbe); -+ reg32_write(0x3c84c124,0xfbe); -+ reg32_write(0x3c84c524,0xfbe); -+ reg32_write(0x3c00010c,0x63); -+ reg32_write(0x3c00410c,0x63); -+ reg32_write(0x3c00810c,0x63); -+ reg32_write(0x3c00c10c,0x63); -+ reg32_write(0x3c01010c,0x63); -+ reg32_write(0x3c01410c,0x63); -+ reg32_write(0x3c01810c,0x63); -+ reg32_write(0x3c01c10c,0x63); -+ reg32_write(0x3c02010c,0x63); -+ reg32_write(0x3c02410c,0x63); -+ reg32_write(0x3c080060,0x3); -+ reg32_write(0x3c0801d4,0x4); -+ reg32_write(0x3c080140,0x0); -+ reg32_write(0x3c080020,0x2ee); -+ reg32_write(0x3c480020,0x64); -+ reg32_write(0x3c880020,0x19); -+ reg32_write(0x3c080220,0x9); -+ reg32_write(0x3c0802c8,0xdc); -+ reg32_write(0x3c04010c,0x5a1); -+ reg32_write(0x3c04050c,0x5a1); -+ reg32_write(0x3c04410c,0x5a1); -+ reg32_write(0x3c04450c,0x5a1); -+ reg32_write(0x3c04810c,0x5a1); -+ reg32_write(0x3c04850c,0x5a1); -+ reg32_write(0x3c04c10c,0x5a1); -+ reg32_write(0x3c04c50c,0x5a1); -+ reg32_write(0x3c4802c8,0xdc); -+ reg32_write(0x3c44010c,0x5a1); -+ reg32_write(0x3c44050c,0x5a1); -+ reg32_write(0x3c44410c,0x5a1); -+ reg32_write(0x3c44450c,0x5a1); -+ reg32_write(0x3c44810c,0x5a1); -+ reg32_write(0x3c44850c,0x5a1); -+ reg32_write(0x3c44c10c,0x5a1); -+ reg32_write(0x3c44c50c,0x5a1); -+ reg32_write(0x3c8802c8,0xdc); -+ reg32_write(0x3c84010c,0x5a1); -+ reg32_write(0x3c84050c,0x5a1); -+ reg32_write(0x3c84410c,0x5a1); -+ reg32_write(0x3c84450c,0x5a1); -+ reg32_write(0x3c84810c,0x5a1); -+ reg32_write(0x3c84850c,0x5a1); -+ reg32_write(0x3c84c10c,0x5a1); -+ reg32_write(0x3c84c50c,0x5a1); -+ reg32_write(0x3c0803e8,0x1); -+ reg32_write(0x3c4803e8,0x1); -+ reg32_write(0x3c8803e8,0x1); -+ reg32_write(0x3c080064,0x1); -+ reg32_write(0x3c480064,0x1); -+ reg32_write(0x3c880064,0x1); -+ reg32_write(0x3c0803c0,0x660); -+ reg32_write(0x3c0803c4,0x0); -+ reg32_write(0x3c0803c8,0x4444); -+ reg32_write(0x3c0803cc,0x8888); -+ reg32_write(0x3c0803d0,0x5665); -+ reg32_write(0x3c0803d4,0x0); -+ reg32_write(0x3c0803d8,0x0); -+ reg32_write(0x3c0803dc,0xf000); -+ reg32_write(0x3c080094,0x0); -+ reg32_write(0x3c0800b4,0x0); -+ reg32_write(0x3c4800b4,0x0); -+ reg32_write(0x3c8800b4,0x0); -+ reg32_write(0x3c08031c,0x21); -+ reg32_write(0x3c48031c,0x21); -+ reg32_write(0x3c88031c,0x21); -+ reg32_write(0x3c080328,0x24); -+ reg32_write(0x3c480328,0x24); -+ reg32_write(0x3c880328,0x24); -+ -+ //enable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); -+ //load the 1D training image -+ ddr_load_train_code(FW_1D_IMAGE); -+ -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xbb8); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); -+ -+ //disable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -+ //Reset MPU and run -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); -+ wait_ddrphy_training_complete(); -+ -+ //configure DDRPHY-FW DMEM structure @clock1... -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ -+ //set the PHY input clock to the desired frequency for pstate 1 -+ reg32_write(0x3038a008,0x7070000); -+ reg32_write(0x3038a004,0x5000000); -+ reg32_write(0x3038a088,0x7070000); -+ reg32_write(0x3038a084,0x2010000); -+ reg32_write(0x303a00ec,0xffff); -+ tmp=reg32_read(0x303a00f8); -+ tmp |= 0x20; -+ reg32_write(0x303a00f8,tmp); -+ reg32_write(0x30389804,0x1000000); -+ -+ //enable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); -+ //load the 1D training image -+ ddr_load_train_code(FW_1D_IMAGE); -+ -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x84); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x84); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x8400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x8400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); -+ -+ //disable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -+ //Reset MPU and run -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); -+ wait_ddrphy_training_complete(); -+ -+ //configure DDRPHY-FW DMEM structure @clock2... -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ -+ //set the PHY input clock to the desired frequency for pstate 2 -+ reg32_write(0x3038a008,0x7070000); -+ reg32_write(0x3038a004,0x2000000); -+ reg32_write(0x3038a088,0x7070000); -+ reg32_write(0x3038a084,0x2010000); -+ reg32_write(0x303a00ec,0xffff); -+ tmp=reg32_read(0x303a00f8); -+ tmp |= 0x20; -+ reg32_write(0x303a00f8,tmp); -+ reg32_write(0x30389804,0x1000000); -+ -+ //enable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); -+ //load the 1D training image -+ ddr_load_train_code(FW_1D_IMAGE); -+ -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x84); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x84); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x8400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x8400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); -+ -+ //disable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -+ //Reset MPU and run -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); -+ wait_ddrphy_training_complete(); -+ -+ //set the PHY input clock to the desired frequency for pstate 0 -+ reg32_write(0x3038a088,0x7070000); -+ reg32_write(0x3038a084,0x4030000); -+ reg32_write(0x303a00ec,0xffff); -+ tmp=reg32_read(0x303a00f8); -+ tmp |= 0x20; -+ reg32_write(0x303a00f8,tmp); -+ reg32_write(0x30360054,0xfa080); -+ reg32_write(0x30360058,0x0); -+ tmp=reg32_read(0x30360050); -+ tmp |= 0x200; -+ reg32_write(0x30360050,tmp); -+ tmp=reg32_read(0x30360050); -+ tmp &= ~0x10; -+ reg32_write(0x30360050,tmp); -+ do{ -+ tmp=reg32_read(0x30360050); -+ if(tmp&0x80000000) break; -+ }while(1); -+ reg32_write(0x30389808,0x1000000); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ -+ -+ //enable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); -+ //load the 2D training image -+ ddr_load_train_code(FW_2D_IMAGE); -+ -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xbb8); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); -+ -+ //disable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -+ //Reset MPU and run -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); -+ wait_ddrphy_training_complete(); -+ -+ //Halt MPU -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); -+ //enable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); -+ -+ //Load firmware PIE image -+ reg32_write(0x3c240000,0x10); -+ reg32_write(0x3c240004,0x400); -+ reg32_write(0x3c240008,0x10e); -+ reg32_write(0x3c24000c,0x0); -+ reg32_write(0x3c240010,0x0); -+ reg32_write(0x3c240014,0x8); -+ reg32_write(0x3c2400a4,0xb); -+ reg32_write(0x3c2400a8,0x480); -+ reg32_write(0x3c2400ac,0x109); -+ reg32_write(0x3c2400b0,0x8); -+ reg32_write(0x3c2400b4,0x448); -+ reg32_write(0x3c2400b8,0x139); -+ reg32_write(0x3c2400bc,0x8); -+ reg32_write(0x3c2400c0,0x478); -+ reg32_write(0x3c2400c4,0x109); -+ reg32_write(0x3c2400c8,0x0); -+ reg32_write(0x3c2400cc,0xe8); -+ reg32_write(0x3c2400d0,0x109); -+ reg32_write(0x3c2400d4,0x2); -+ reg32_write(0x3c2400d8,0x10); -+ reg32_write(0x3c2400dc,0x139); -+ reg32_write(0x3c2400e0,0xf); -+ reg32_write(0x3c2400e4,0x7c0); -+ reg32_write(0x3c2400e8,0x139); -+ reg32_write(0x3c2400ec,0x44); -+ reg32_write(0x3c2400f0,0x630); -+ reg32_write(0x3c2400f4,0x159); -+ reg32_write(0x3c2400f8,0x14f); -+ reg32_write(0x3c2400fc,0x630); -+ reg32_write(0x3c240100,0x159); -+ reg32_write(0x3c240104,0x47); -+ reg32_write(0x3c240108,0x630); -+ reg32_write(0x3c24010c,0x149); -+ reg32_write(0x3c240110,0x4f); -+ reg32_write(0x3c240114,0x630); -+ reg32_write(0x3c240118,0x179); -+ reg32_write(0x3c24011c,0x8); -+ reg32_write(0x3c240120,0xe0); -+ reg32_write(0x3c240124,0x109); -+ reg32_write(0x3c240128,0x0); -+ reg32_write(0x3c24012c,0x7c8); -+ reg32_write(0x3c240130,0x109); -+ reg32_write(0x3c240134,0x0); -+ reg32_write(0x3c240138,0x1); -+ reg32_write(0x3c24013c,0x8); -+ reg32_write(0x3c240140,0x0); -+ reg32_write(0x3c240144,0x45a); -+ reg32_write(0x3c240148,0x9); -+ reg32_write(0x3c24014c,0x0); -+ reg32_write(0x3c240150,0x448); -+ reg32_write(0x3c240154,0x109); -+ reg32_write(0x3c240158,0x40); -+ reg32_write(0x3c24015c,0x630); -+ reg32_write(0x3c240160,0x179); -+ reg32_write(0x3c240164,0x1); -+ reg32_write(0x3c240168,0x618); -+ reg32_write(0x3c24016c,0x109); -+ reg32_write(0x3c240170,0x40c0); -+ reg32_write(0x3c240174,0x630); -+ reg32_write(0x3c240178,0x149); -+ reg32_write(0x3c24017c,0x8); -+ reg32_write(0x3c240180,0x4); -+ reg32_write(0x3c240184,0x48); -+ reg32_write(0x3c240188,0x4040); -+ reg32_write(0x3c24018c,0x630); -+ reg32_write(0x3c240190,0x149); -+ reg32_write(0x3c240194,0x0); -+ reg32_write(0x3c240198,0x4); -+ reg32_write(0x3c24019c,0x48); -+ reg32_write(0x3c2401a0,0x40); -+ reg32_write(0x3c2401a4,0x630); -+ reg32_write(0x3c2401a8,0x149); -+ reg32_write(0x3c2401ac,0x10); -+ reg32_write(0x3c2401b0,0x4); -+ reg32_write(0x3c2401b4,0x18); -+ reg32_write(0x3c2401b8,0x0); -+ reg32_write(0x3c2401bc,0x4); -+ reg32_write(0x3c2401c0,0x78); -+ reg32_write(0x3c2401c4,0x549); -+ reg32_write(0x3c2401c8,0x630); -+ reg32_write(0x3c2401cc,0x159); -+ reg32_write(0x3c2401d0,0xd49); -+ reg32_write(0x3c2401d4,0x630); -+ reg32_write(0x3c2401d8,0x159); -+ reg32_write(0x3c2401dc,0x94a); -+ reg32_write(0x3c2401e0,0x630); -+ reg32_write(0x3c2401e4,0x159); -+ reg32_write(0x3c2401e8,0x441); -+ reg32_write(0x3c2401ec,0x630); -+ reg32_write(0x3c2401f0,0x149); -+ reg32_write(0x3c2401f4,0x42); -+ reg32_write(0x3c2401f8,0x630); -+ reg32_write(0x3c2401fc,0x149); -+ reg32_write(0x3c240200,0x1); -+ reg32_write(0x3c240204,0x630); -+ reg32_write(0x3c240208,0x149); -+ reg32_write(0x3c24020c,0x0); -+ reg32_write(0x3c240210,0xe0); -+ reg32_write(0x3c240214,0x109); -+ reg32_write(0x3c240218,0xa); -+ reg32_write(0x3c24021c,0x10); -+ reg32_write(0x3c240220,0x109); -+ reg32_write(0x3c240224,0x9); -+ reg32_write(0x3c240228,0x3c0); -+ reg32_write(0x3c24022c,0x149); -+ reg32_write(0x3c240230,0x9); -+ reg32_write(0x3c240234,0x3c0); -+ reg32_write(0x3c240238,0x159); -+ reg32_write(0x3c24023c,0x18); -+ reg32_write(0x3c240240,0x10); -+ reg32_write(0x3c240244,0x109); -+ reg32_write(0x3c240248,0x0); -+ reg32_write(0x3c24024c,0x3c0); -+ reg32_write(0x3c240250,0x109); -+ reg32_write(0x3c240254,0x18); -+ reg32_write(0x3c240258,0x4); -+ reg32_write(0x3c24025c,0x48); -+ reg32_write(0x3c240260,0x18); -+ reg32_write(0x3c240264,0x4); -+ reg32_write(0x3c240268,0x58); -+ reg32_write(0x3c24026c,0xa); -+ reg32_write(0x3c240270,0x10); -+ reg32_write(0x3c240274,0x109); -+ reg32_write(0x3c240278,0x2); -+ reg32_write(0x3c24027c,0x10); -+ reg32_write(0x3c240280,0x109); -+ reg32_write(0x3c240284,0x5); -+ reg32_write(0x3c240288,0x7c0); -+ reg32_write(0x3c24028c,0x109); -+ reg32_write(0x3c240290,0x10); -+ reg32_write(0x3c240294,0x10); -+ reg32_write(0x3c240298,0x109); -+ reg32_write(0x3c100000,0x811); -+ reg32_write(0x3c100080,0x880); -+ reg32_write(0x3c100100,0x0); -+ reg32_write(0x3c100180,0x0); -+ reg32_write(0x3c100004,0x4008); -+ reg32_write(0x3c100084,0x83); -+ reg32_write(0x3c100104,0x4f); -+ reg32_write(0x3c100184,0x0); -+ reg32_write(0x3c100008,0x4040); -+ reg32_write(0x3c100088,0x83); -+ reg32_write(0x3c100108,0x51); -+ reg32_write(0x3c100188,0x0); -+ reg32_write(0x3c10000c,0x811); -+ reg32_write(0x3c10008c,0x880); -+ reg32_write(0x3c10010c,0x0); -+ reg32_write(0x3c10018c,0x0); -+ reg32_write(0x3c100010,0x720); -+ reg32_write(0x3c100090,0xf); -+ reg32_write(0x3c100110,0x1740); -+ reg32_write(0x3c100190,0x0); -+ reg32_write(0x3c100014,0x16); -+ reg32_write(0x3c100094,0x83); -+ reg32_write(0x3c100114,0x4b); -+ reg32_write(0x3c100194,0x0); -+ reg32_write(0x3c100018,0x716); -+ reg32_write(0x3c100098,0xf); -+ reg32_write(0x3c100118,0x2001); -+ reg32_write(0x3c100198,0x0); -+ reg32_write(0x3c10001c,0x716); -+ reg32_write(0x3c10009c,0xf); -+ reg32_write(0x3c10011c,0x2800); -+ reg32_write(0x3c10019c,0x0); -+ reg32_write(0x3c100020,0x716); -+ reg32_write(0x3c1000a0,0xf); -+ reg32_write(0x3c100120,0xf00); -+ reg32_write(0x3c1001a0,0x0); -+ reg32_write(0x3c100024,0x720); -+ reg32_write(0x3c1000a4,0xf); -+ reg32_write(0x3c100124,0x1400); -+ reg32_write(0x3c1001a4,0x0); -+ reg32_write(0x3c100028,0xe08); -+ reg32_write(0x3c1000a8,0xc15); -+ reg32_write(0x3c100128,0x0); -+ reg32_write(0x3c1001a8,0x0); -+ reg32_write(0x3c10002c,0x623); -+ reg32_write(0x3c1000ac,0x15); -+ reg32_write(0x3c10012c,0x0); -+ reg32_write(0x3c1001ac,0x0); -+ reg32_write(0x3c100030,0x4028); -+ reg32_write(0x3c1000b0,0x80); -+ reg32_write(0x3c100130,0x0); -+ reg32_write(0x3c1001b0,0x0); -+ reg32_write(0x3c100034,0xe08); -+ reg32_write(0x3c1000b4,0xc1a); -+ reg32_write(0x3c100134,0x0); -+ reg32_write(0x3c1001b4,0x0); -+ reg32_write(0x3c100038,0x623); -+ reg32_write(0x3c1000b8,0x1a); -+ reg32_write(0x3c100138,0x0); -+ reg32_write(0x3c1001b8,0x0); -+ reg32_write(0x3c10003c,0x4040); -+ reg32_write(0x3c1000bc,0x80); -+ reg32_write(0x3c10013c,0x0); -+ reg32_write(0x3c1001bc,0x0); -+ reg32_write(0x3c100040,0x2604); -+ reg32_write(0x3c1000c0,0x15); -+ reg32_write(0x3c100140,0x0); -+ reg32_write(0x3c1001c0,0x0); -+ reg32_write(0x3c100044,0x708); -+ reg32_write(0x3c1000c4,0x5); -+ reg32_write(0x3c100144,0x0); -+ reg32_write(0x3c1001c4,0x2002); -+ reg32_write(0x3c100048,0x8); -+ reg32_write(0x3c1000c8,0x80); -+ reg32_write(0x3c100148,0x0); -+ reg32_write(0x3c1001c8,0x0); -+ reg32_write(0x3c10004c,0x2604); -+ reg32_write(0x3c1000cc,0x1a); -+ reg32_write(0x3c10014c,0x0); -+ reg32_write(0x3c1001cc,0x0); -+ reg32_write(0x3c100050,0x708); -+ reg32_write(0x3c1000d0,0xa); -+ reg32_write(0x3c100150,0x0); -+ reg32_write(0x3c1001d0,0x2002); -+ reg32_write(0x3c100054,0x4040); -+ reg32_write(0x3c1000d4,0x80); -+ reg32_write(0x3c100154,0x0); -+ reg32_write(0x3c1001d4,0x0); -+ reg32_write(0x3c100058,0x60a); -+ reg32_write(0x3c1000d8,0x15); -+ reg32_write(0x3c100158,0x1200); -+ reg32_write(0x3c1001d8,0x0); -+ reg32_write(0x3c10005c,0x61a); -+ reg32_write(0x3c1000dc,0x15); -+ reg32_write(0x3c10015c,0x1300); -+ reg32_write(0x3c1001dc,0x0); -+ reg32_write(0x3c100060,0x60a); -+ reg32_write(0x3c1000e0,0x1a); -+ reg32_write(0x3c100160,0x1200); -+ reg32_write(0x3c1001e0,0x0); -+ reg32_write(0x3c100064,0x642); -+ reg32_write(0x3c1000e4,0x1a); -+ reg32_write(0x3c100164,0x1300); -+ reg32_write(0x3c1001e4,0x0); -+ reg32_write(0x3c100068,0x4808); -+ reg32_write(0x3c1000e8,0x880); -+ reg32_write(0x3c100168,0x0); -+ reg32_write(0x3c1001e8,0x0); -+ reg32_write(0x3c24029c,0x0); -+ reg32_write(0x3c2402a0,0x790); -+ reg32_write(0x3c2402a4,0x11a); -+ reg32_write(0x3c2402a8,0x8); -+ reg32_write(0x3c2402ac,0x7aa); -+ reg32_write(0x3c2402b0,0x2a); -+ reg32_write(0x3c2402b4,0x10); -+ reg32_write(0x3c2402b8,0x7b2); -+ reg32_write(0x3c2402bc,0x2a); -+ reg32_write(0x3c2402c0,0x0); -+ reg32_write(0x3c2402c4,0x7c8); -+ reg32_write(0x3c2402c8,0x109); -+ reg32_write(0x3c2402cc,0x10); -+ reg32_write(0x3c2402d0,0x2a8); -+ reg32_write(0x3c2402d4,0x129); -+ reg32_write(0x3c2402d8,0x8); -+ reg32_write(0x3c2402dc,0x370); -+ reg32_write(0x3c2402e0,0x129); -+ reg32_write(0x3c2402e4,0xa); -+ reg32_write(0x3c2402e8,0x3c8); -+ reg32_write(0x3c2402ec,0x1a9); -+ reg32_write(0x3c2402f0,0xc); -+ reg32_write(0x3c2402f4,0x408); -+ reg32_write(0x3c2402f8,0x199); -+ reg32_write(0x3c2402fc,0x14); -+ reg32_write(0x3c240300,0x790); -+ reg32_write(0x3c240304,0x11a); -+ reg32_write(0x3c240308,0x8); -+ reg32_write(0x3c24030c,0x4); -+ reg32_write(0x3c240310,0x18); -+ reg32_write(0x3c240314,0xe); -+ reg32_write(0x3c240318,0x408); -+ reg32_write(0x3c24031c,0x199); -+ reg32_write(0x3c240320,0x8); -+ reg32_write(0x3c240324,0x8568); -+ reg32_write(0x3c240328,0x108); -+ reg32_write(0x3c24032c,0x18); -+ reg32_write(0x3c240330,0x790); -+ reg32_write(0x3c240334,0x16a); -+ reg32_write(0x3c240338,0x8); -+ reg32_write(0x3c24033c,0x1d8); -+ reg32_write(0x3c240340,0x169); -+ reg32_write(0x3c240344,0x10); -+ reg32_write(0x3c240348,0x8558); -+ reg32_write(0x3c24034c,0x168); -+ reg32_write(0x3c240350,0x70); -+ reg32_write(0x3c240354,0x788); -+ reg32_write(0x3c240358,0x16a); -+ reg32_write(0x3c24035c,0x1ff8); -+ reg32_write(0x3c240360,0x85a8); -+ reg32_write(0x3c240364,0x1e8); -+ reg32_write(0x3c240368,0x50); -+ reg32_write(0x3c24036c,0x798); -+ reg32_write(0x3c240370,0x16a); -+ reg32_write(0x3c240374,0x60); -+ reg32_write(0x3c240378,0x7a0); -+ reg32_write(0x3c24037c,0x16a); -+ reg32_write(0x3c240380,0x8); -+ reg32_write(0x3c240384,0x8310); -+ reg32_write(0x3c240388,0x168); -+ reg32_write(0x3c24038c,0x8); -+ reg32_write(0x3c240390,0xa310); -+ reg32_write(0x3c240394,0x168); -+ reg32_write(0x3c240398,0xa); -+ reg32_write(0x3c24039c,0x408); -+ reg32_write(0x3c2403a0,0x169); -+ reg32_write(0x3c2403a4,0x6e); -+ reg32_write(0x3c2403a8,0x0); -+ reg32_write(0x3c2403ac,0x68); -+ reg32_write(0x3c2403b0,0x0); -+ reg32_write(0x3c2403b4,0x408); -+ reg32_write(0x3c2403b8,0x169); -+ reg32_write(0x3c2403bc,0x0); -+ reg32_write(0x3c2403c0,0x8310); -+ reg32_write(0x3c2403c4,0x168); -+ reg32_write(0x3c2403c8,0x0); -+ reg32_write(0x3c2403cc,0xa310); -+ reg32_write(0x3c2403d0,0x168); -+ reg32_write(0x3c2403d4,0x1ff8); -+ reg32_write(0x3c2403d8,0x85a8); -+ reg32_write(0x3c2403dc,0x1e8); -+ reg32_write(0x3c2403e0,0x68); -+ reg32_write(0x3c2403e4,0x798); -+ reg32_write(0x3c2403e8,0x16a); -+ reg32_write(0x3c2403ec,0x78); -+ reg32_write(0x3c2403f0,0x7a0); -+ reg32_write(0x3c2403f4,0x16a); -+ reg32_write(0x3c2403f8,0x68); -+ reg32_write(0x3c2403fc,0x790); -+ reg32_write(0x3c240400,0x16a); -+ reg32_write(0x3c240404,0x8); -+ reg32_write(0x3c240408,0x8b10); -+ reg32_write(0x3c24040c,0x168); -+ reg32_write(0x3c240410,0x8); -+ reg32_write(0x3c240414,0xab10); -+ reg32_write(0x3c240418,0x168); -+ reg32_write(0x3c24041c,0xa); -+ reg32_write(0x3c240420,0x408); -+ reg32_write(0x3c240424,0x169); -+ reg32_write(0x3c240428,0x58); -+ reg32_write(0x3c24042c,0x0); -+ reg32_write(0x3c240430,0x68); -+ reg32_write(0x3c240434,0x0); -+ reg32_write(0x3c240438,0x408); -+ reg32_write(0x3c24043c,0x169); -+ reg32_write(0x3c240440,0x0); -+ reg32_write(0x3c240444,0x8b10); -+ reg32_write(0x3c240448,0x168); -+ reg32_write(0x3c24044c,0x0); -+ reg32_write(0x3c240450,0xab10); -+ reg32_write(0x3c240454,0x168); -+ reg32_write(0x3c240458,0x0); -+ reg32_write(0x3c24045c,0x1d8); -+ reg32_write(0x3c240460,0x169); -+ reg32_write(0x3c240464,0x80); -+ reg32_write(0x3c240468,0x790); -+ reg32_write(0x3c24046c,0x16a); -+ reg32_write(0x3c240470,0x18); -+ reg32_write(0x3c240474,0x7aa); -+ reg32_write(0x3c240478,0x6a); -+ reg32_write(0x3c24047c,0xa); -+ reg32_write(0x3c240480,0x0); -+ reg32_write(0x3c240484,0x1e9); -+ reg32_write(0x3c240488,0x8); -+ reg32_write(0x3c24048c,0x8080); -+ reg32_write(0x3c240490,0x108); -+ reg32_write(0x3c240494,0xf); -+ reg32_write(0x3c240498,0x408); -+ reg32_write(0x3c24049c,0x169); -+ reg32_write(0x3c2404a0,0xc); -+ reg32_write(0x3c2404a4,0x0); -+ reg32_write(0x3c2404a8,0x68); -+ reg32_write(0x3c2404ac,0x9); -+ reg32_write(0x3c2404b0,0x0); -+ reg32_write(0x3c2404b4,0x1a9); -+ reg32_write(0x3c2404b8,0x0); -+ reg32_write(0x3c2404bc,0x408); -+ reg32_write(0x3c2404c0,0x169); -+ reg32_write(0x3c2404c4,0x0); -+ reg32_write(0x3c2404c8,0x8080); -+ reg32_write(0x3c2404cc,0x108); -+ reg32_write(0x3c2404d0,0x8); -+ reg32_write(0x3c2404d4,0x7aa); -+ reg32_write(0x3c2404d8,0x6a); -+ reg32_write(0x3c2404dc,0x0); -+ reg32_write(0x3c2404e0,0x8568); -+ reg32_write(0x3c2404e4,0x108); -+ reg32_write(0x3c2404e8,0xb7); -+ reg32_write(0x3c2404ec,0x790); -+ reg32_write(0x3c2404f0,0x16a); -+ reg32_write(0x3c2404f4,0x1f); -+ reg32_write(0x3c2404f8,0x0); -+ reg32_write(0x3c2404fc,0x68); -+ reg32_write(0x3c240500,0x8); -+ reg32_write(0x3c240504,0x8558); -+ reg32_write(0x3c240508,0x168); -+ reg32_write(0x3c24050c,0xf); -+ reg32_write(0x3c240510,0x408); -+ reg32_write(0x3c240514,0x169); -+ reg32_write(0x3c240518,0xc); -+ reg32_write(0x3c24051c,0x0); -+ reg32_write(0x3c240520,0x68); -+ reg32_write(0x3c240524,0x0); -+ reg32_write(0x3c240528,0x408); -+ reg32_write(0x3c24052c,0x169); -+ reg32_write(0x3c240530,0x0); -+ reg32_write(0x3c240534,0x8558); -+ reg32_write(0x3c240538,0x168); -+ reg32_write(0x3c24053c,0x8); -+ reg32_write(0x3c240540,0x3c8); -+ reg32_write(0x3c240544,0x1a9); -+ reg32_write(0x3c240548,0x3); -+ reg32_write(0x3c24054c,0x370); -+ reg32_write(0x3c240550,0x129); -+ reg32_write(0x3c240554,0x20); -+ reg32_write(0x3c240558,0x2aa); -+ reg32_write(0x3c24055c,0x9); -+ reg32_write(0x3c240560,0x0); -+ reg32_write(0x3c240564,0x400); -+ reg32_write(0x3c240568,0x10e); -+ reg32_write(0x3c24056c,0x8); -+ reg32_write(0x3c240570,0xe8); -+ reg32_write(0x3c240574,0x109); -+ reg32_write(0x3c240578,0x0); -+ reg32_write(0x3c24057c,0x8140); -+ reg32_write(0x3c240580,0x10c); -+ reg32_write(0x3c240584,0x10); -+ reg32_write(0x3c240588,0x8138); -+ reg32_write(0x3c24058c,0x10c); -+ reg32_write(0x3c240590,0x8); -+ reg32_write(0x3c240594,0x7c8); -+ reg32_write(0x3c240598,0x101); -+ reg32_write(0x3c24059c,0x8); -+ reg32_write(0x3c2405a0,0x0); -+ reg32_write(0x3c2405a4,0x8); -+ reg32_write(0x3c2405a8,0x8); -+ reg32_write(0x3c2405ac,0x448); -+ reg32_write(0x3c2405b0,0x109); -+ reg32_write(0x3c2405b4,0xf); -+ reg32_write(0x3c2405b8,0x7c0); -+ reg32_write(0x3c2405bc,0x109); -+ reg32_write(0x3c2405c0,0x0); -+ reg32_write(0x3c2405c4,0xe8); -+ reg32_write(0x3c2405c8,0x109); -+ reg32_write(0x3c2405cc,0x47); -+ reg32_write(0x3c2405d0,0x630); -+ reg32_write(0x3c2405d4,0x109); -+ reg32_write(0x3c2405d8,0x8); -+ reg32_write(0x3c2405dc,0x618); -+ reg32_write(0x3c2405e0,0x109); -+ reg32_write(0x3c2405e4,0x8); -+ reg32_write(0x3c2405e8,0xe0); -+ reg32_write(0x3c2405ec,0x109); -+ reg32_write(0x3c2405f0,0x0); -+ reg32_write(0x3c2405f4,0x7c8); -+ reg32_write(0x3c2405f8,0x109); -+ reg32_write(0x3c2405fc,0x8); -+ reg32_write(0x3c240600,0x8140); -+ reg32_write(0x3c240604,0x10c); -+ reg32_write(0x3c240608,0x0); -+ reg32_write(0x3c24060c,0x1); -+ reg32_write(0x3c240610,0x8); -+ reg32_write(0x3c240614,0x8); -+ reg32_write(0x3c240618,0x4); -+ reg32_write(0x3c24061c,0x8); -+ reg32_write(0x3c240620,0x8); -+ reg32_write(0x3c240624,0x7c8); -+ reg32_write(0x3c240628,0x101); -+ reg32_write(0x3c240018,0x0); -+ reg32_write(0x3c24001c,0x0); -+ reg32_write(0x3c240020,0x8); -+ reg32_write(0x3c240024,0x0); -+ reg32_write(0x3c240028,0x0); -+ reg32_write(0x3c24002c,0x0); -+ reg32_write(0x3c34039c,0x400); -+ reg32_write(0x3c24005c,0x0); -+ reg32_write(0x3c24007c,0x2a); -+ reg32_write(0x3c240098,0x6a); -+ reg32_write(0x3c100340,0x0); -+ reg32_write(0x3c100344,0x101); -+ reg32_write(0x3c100348,0x105); -+ reg32_write(0x3c10034c,0x107); -+ reg32_write(0x3c100350,0x10f); -+ reg32_write(0x3c100354,0x202); -+ reg32_write(0x3c100358,0x20a); -+ reg32_write(0x3c10035c,0x20b); -+ reg32_write(0x3c0800e8,0x2); -+ reg32_write(0x3c08002c,0x5d); -+ reg32_write(0x3c080030,0xbb); -+ reg32_write(0x3c080034,0x753); -+ reg32_write(0x3c080038,0x2c); -+ reg32_write(0x3c48002c,0xc); -+ reg32_write(0x3c480030,0x19); -+ reg32_write(0x3c480034,0xfa); -+ reg32_write(0x3c480038,0x10); -+ reg32_write(0x3c88002c,0x3); -+ reg32_write(0x3c880030,0x6); -+ reg32_write(0x3c880034,0x3e); -+ reg32_write(0x3c880038,0x10); -+ reg32_write(0x3c240030,0x0); -+ reg32_write(0x3c240034,0x173); -+ reg32_write(0x3c240038,0x60); -+ reg32_write(0x3c24003c,0x6110); -+ reg32_write(0x3c240040,0x2152); -+ reg32_write(0x3c240044,0xdfbd); -+ reg32_write(0x3c240048,0x60); -+ reg32_write(0x3c24004c,0x6152); -+ reg32_write(0x3c080040,0x5a); -+ reg32_write(0x3c080044,0x3); -+ reg32_write(0x3c480040,0x5a); -+ reg32_write(0x3c480044,0x3); -+ reg32_write(0x3c880040,0x5a); -+ reg32_write(0x3c880044,0x3); -+ reg32_write(0x3c100200,0xe0); -+ reg32_write(0x3c100204,0x12); -+ reg32_write(0x3c100208,0xe0); -+ reg32_write(0x3c10020c,0x12); -+ reg32_write(0x3c100210,0xe0); -+ reg32_write(0x3c100214,0x12); -+ reg32_write(0x3c500200,0xe0); -+ reg32_write(0x3c500204,0x12); -+ reg32_write(0x3c500208,0xe0); -+ reg32_write(0x3c50020c,0x12); -+ reg32_write(0x3c500210,0xe0); -+ reg32_write(0x3c500214,0x12); -+ reg32_write(0x3c900200,0xe0); -+ reg32_write(0x3c900204,0x12); -+ reg32_write(0x3c900208,0xe0); -+ reg32_write(0x3c90020c,0x12); -+ reg32_write(0x3c900210,0xe0); -+ reg32_write(0x3c900214,0x12); -+ reg32_write(0x3c1003f4,0xf); -+ reg32_write(0x3c040044,0x1); -+ reg32_write(0x3c040048,0x1); -+ reg32_write(0x3c04004c,0x180); -+ reg32_write(0x3c040060,0x1); -+ reg32_write(0x3c040008,0x6209); -+ reg32_write(0x3c0402c8,0x1); -+ reg32_write(0x3c0406d0,0x1); -+ reg32_write(0x3c040ad0,0x1); -+ reg32_write(0x3c040ed0,0x1); -+ reg32_write(0x3c0412d0,0x1); -+ reg32_write(0x3c0416d0,0x1); -+ reg32_write(0x3c041ad0,0x1); -+ reg32_write(0x3c041ed0,0x1); -+ reg32_write(0x3c0422d0,0x1); -+ reg32_write(0x3c044044,0x1); -+ reg32_write(0x3c044048,0x1); -+ reg32_write(0x3c04404c,0x180); -+ reg32_write(0x3c044060,0x1); -+ reg32_write(0x3c044008,0x6209); -+ reg32_write(0x3c0442c8,0x1); -+ reg32_write(0x3c0446d0,0x1); -+ reg32_write(0x3c044ad0,0x1); -+ reg32_write(0x3c044ed0,0x1); -+ reg32_write(0x3c0452d0,0x1); -+ reg32_write(0x3c0456d0,0x1); -+ reg32_write(0x3c045ad0,0x1); -+ reg32_write(0x3c045ed0,0x1); -+ reg32_write(0x3c0462d0,0x1); -+ reg32_write(0x3c048044,0x1); -+ reg32_write(0x3c048048,0x1); -+ reg32_write(0x3c04804c,0x180); -+ reg32_write(0x3c048060,0x1); -+ reg32_write(0x3c048008,0x6209); -+ reg32_write(0x3c0482c8,0x1); -+ reg32_write(0x3c0486d0,0x1); -+ reg32_write(0x3c048ad0,0x1); -+ reg32_write(0x3c048ed0,0x1); -+ reg32_write(0x3c0492d0,0x1); -+ reg32_write(0x3c0496d0,0x1); -+ reg32_write(0x3c049ad0,0x1); -+ reg32_write(0x3c049ed0,0x1); -+ reg32_write(0x3c04a2d0,0x1); -+ reg32_write(0x3c04c044,0x1); -+ reg32_write(0x3c04c048,0x1); -+ reg32_write(0x3c04c04c,0x180); -+ reg32_write(0x3c04c060,0x1); -+ reg32_write(0x3c04c008,0x6209); -+ reg32_write(0x3c04c2c8,0x1); -+ reg32_write(0x3c04c6d0,0x1); -+ reg32_write(0x3c04cad0,0x1); -+ reg32_write(0x3c04ced0,0x1); -+ reg32_write(0x3c04d2d0,0x1); -+ reg32_write(0x3c04d6d0,0x1); -+ reg32_write(0x3c04dad0,0x1); -+ reg32_write(0x3c04ded0,0x1); -+ reg32_write(0x3c04e2d0,0x1); -+ reg32_write(0x3c0800e8,0x2); -+ reg32_write(0x3c300200,0x2); -+ //customer Post Train -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001); -+ /* -+ * CalBusy.0 =1, indicates the calibrator is actively calibrating. -+ * Wait Calibrating done. -+ */ -+ tmp_t = 1; -+ while(tmp_t) { -+ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097); -+ tmp_t = tmp & 0x01; -+ } -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); -+ //disable APB bus to access DDRPHY RAM -+ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); -+} ++/* ++ * Copyright 2017 NXP ++ * ++ * SPDX-License-Identifier: GPL-2.0+ ++ * ++ * Generated code from MX8M_DDR_tool ++ * Align with uboot-imx_v2017.03_4.9.51_imx8m_ga ++ */ ++ ++#include ++#include ++#include ++#include ++#include "ddr.h" ++ ++extern void wait_ddrphy_training_complete(void); ++void ddr_cfg_phy(void) { ++ unsigned int tmp, tmp_t; ++ ++ //Init DDRPHY register... ++ reg32_write(0x3c04017c,0x1ff); ++ reg32_write(0x3c04057c,0x1ff); ++ reg32_write(0x3c04417c,0x1ff); ++ reg32_write(0x3c04457c,0x1ff); ++ reg32_write(0x3c04817c,0x1ff); ++ reg32_write(0x3c04857c,0x1ff); ++ reg32_write(0x3c04c17c,0x1ff); ++ reg32_write(0x3c04c57c,0x1ff); ++ reg32_write(0x3c44017c,0x1ff); ++ reg32_write(0x3c44057c,0x1ff); ++ reg32_write(0x3c44417c,0x1ff); ++ reg32_write(0x3c44457c,0x1ff); ++ reg32_write(0x3c44817c,0x1ff); ++ reg32_write(0x3c44857c,0x1ff); ++ reg32_write(0x3c44c17c,0x1ff); ++ reg32_write(0x3c44c57c,0x1ff); ++ reg32_write(0x3c84017c,0x1ff); ++ reg32_write(0x3c84057c,0x1ff); ++ reg32_write(0x3c84417c,0x1ff); ++ reg32_write(0x3c84457c,0x1ff); ++ reg32_write(0x3c84817c,0x1ff); ++ reg32_write(0x3c84857c,0x1ff); ++ reg32_write(0x3c84c17c,0x1ff); ++ reg32_write(0x3c84c57c,0x1ff); ++ reg32_write(0x3c000154,0x1ff); ++ reg32_write(0x3c004154,0x1ff); ++ reg32_write(0x3c008154,0x1ff); ++ reg32_write(0x3c00c154,0x1ff); ++ reg32_write(0x3c010154,0x1ff); ++ reg32_write(0x3c014154,0x1ff); ++ reg32_write(0x3c018154,0x1ff); ++ reg32_write(0x3c01c154,0x1ff); ++ reg32_write(0x3c020154,0x1ff); ++ reg32_write(0x3c024154,0x1ff); ++ reg32_write(0x3c080314,0x19); ++ reg32_write(0x3c480314,0x7); ++ reg32_write(0x3c880314,0x7); ++ reg32_write(0x3c0800b8,0x2); ++ reg32_write(0x3c4800b8,0x2); ++ reg32_write(0x3c8800b8,0x2); ++ reg32_write(0x3c240810,0x0); ++ reg32_write(0x3c640810,0x0); ++ reg32_write(0x3ca40810,0x0); ++ reg32_write(0x3c080090,0xab); ++ reg32_write(0x3c0800e8,0x0); ++ reg32_write(0x3c480090,0xab); ++ reg32_write(0x3c0800e8,0x0); ++ reg32_write(0x3c880090,0xab); ++ reg32_write(0x3c0800e8,0x0); ++ reg32_write(0x3c080158,0x3); ++ reg32_write(0x3c480158,0xa); ++ reg32_write(0x3c880158,0xa); ++ reg32_write(0x3c040134,0xe00); ++ reg32_write(0x3c040534,0xe00); ++ reg32_write(0x3c044134,0xe00); ++ reg32_write(0x3c044534,0xe00); ++ reg32_write(0x3c048134,0xe00); ++ reg32_write(0x3c048534,0xe00); ++ reg32_write(0x3c04c134,0xe00); ++ reg32_write(0x3c04c534,0xe00); ++ reg32_write(0x3c440134,0xe00); ++ reg32_write(0x3c440534,0xe00); ++ reg32_write(0x3c444134,0xe00); ++ reg32_write(0x3c444534,0xe00); ++ reg32_write(0x3c448134,0xe00); ++ reg32_write(0x3c448534,0xe00); ++ reg32_write(0x3c44c134,0xe00); ++ reg32_write(0x3c44c534,0xe00); ++ reg32_write(0x3c840134,0xe00); ++ reg32_write(0x3c840534,0xe00); ++ reg32_write(0x3c844134,0xe00); ++ reg32_write(0x3c844534,0xe00); ++ reg32_write(0x3c848134,0xe00); ++ reg32_write(0x3c848534,0xe00); ++ reg32_write(0x3c84c134,0xe00); ++ reg32_write(0x3c84c534,0xe00); ++ reg32_write(0x3c040124,0xfbe); ++ reg32_write(0x3c040524,0xfbe); ++ reg32_write(0x3c044124,0xfbe); ++ reg32_write(0x3c044524,0xfbe); ++ reg32_write(0x3c048124,0xfbe); ++ reg32_write(0x3c048524,0xfbe); ++ reg32_write(0x3c04c124,0xfbe); ++ reg32_write(0x3c04c524,0xfbe); ++ reg32_write(0x3c440124,0xfbe); ++ reg32_write(0x3c440524,0xfbe); ++ reg32_write(0x3c444124,0xfbe); ++ reg32_write(0x3c444524,0xfbe); ++ reg32_write(0x3c448124,0xfbe); ++ reg32_write(0x3c448524,0xfbe); ++ reg32_write(0x3c44c124,0xfbe); ++ reg32_write(0x3c44c524,0xfbe); ++ reg32_write(0x3c840124,0xfbe); ++ reg32_write(0x3c840524,0xfbe); ++ reg32_write(0x3c844124,0xfbe); ++ reg32_write(0x3c844524,0xfbe); ++ reg32_write(0x3c848124,0xfbe); ++ reg32_write(0x3c848524,0xfbe); ++ reg32_write(0x3c84c124,0xfbe); ++ reg32_write(0x3c84c524,0xfbe); ++ reg32_write(0x3c00010c,0x63); ++ reg32_write(0x3c00410c,0x63); ++ reg32_write(0x3c00810c,0x63); ++ reg32_write(0x3c00c10c,0x63); ++ reg32_write(0x3c01010c,0x63); ++ reg32_write(0x3c01410c,0x63); ++ reg32_write(0x3c01810c,0x63); ++ reg32_write(0x3c01c10c,0x63); ++ reg32_write(0x3c02010c,0x63); ++ reg32_write(0x3c02410c,0x63); ++ reg32_write(0x3c080060,0x3); ++ reg32_write(0x3c0801d4,0x4); ++ reg32_write(0x3c080140,0x0); ++ reg32_write(0x3c080020,0x2ee); ++ reg32_write(0x3c480020,0x64); ++ reg32_write(0x3c880020,0x19); ++ reg32_write(0x3c080220,0x9); ++ reg32_write(0x3c0802c8,0xdc); ++ reg32_write(0x3c04010c,0x5a1); ++ reg32_write(0x3c04050c,0x5a1); ++ reg32_write(0x3c04410c,0x5a1); ++ reg32_write(0x3c04450c,0x5a1); ++ reg32_write(0x3c04810c,0x5a1); ++ reg32_write(0x3c04850c,0x5a1); ++ reg32_write(0x3c04c10c,0x5a1); ++ reg32_write(0x3c04c50c,0x5a1); ++ reg32_write(0x3c4802c8,0xdc); ++ reg32_write(0x3c44010c,0x5a1); ++ reg32_write(0x3c44050c,0x5a1); ++ reg32_write(0x3c44410c,0x5a1); ++ reg32_write(0x3c44450c,0x5a1); ++ reg32_write(0x3c44810c,0x5a1); ++ reg32_write(0x3c44850c,0x5a1); ++ reg32_write(0x3c44c10c,0x5a1); ++ reg32_write(0x3c44c50c,0x5a1); ++ reg32_write(0x3c8802c8,0xdc); ++ reg32_write(0x3c84010c,0x5a1); ++ reg32_write(0x3c84050c,0x5a1); ++ reg32_write(0x3c84410c,0x5a1); ++ reg32_write(0x3c84450c,0x5a1); ++ reg32_write(0x3c84810c,0x5a1); ++ reg32_write(0x3c84850c,0x5a1); ++ reg32_write(0x3c84c10c,0x5a1); ++ reg32_write(0x3c84c50c,0x5a1); ++ reg32_write(0x3c0803e8,0x1); ++ reg32_write(0x3c4803e8,0x1); ++ reg32_write(0x3c8803e8,0x1); ++ reg32_write(0x3c080064,0x1); ++ reg32_write(0x3c480064,0x1); ++ reg32_write(0x3c880064,0x1); ++ reg32_write(0x3c0803c0,0x660); ++ reg32_write(0x3c0803c4,0x0); ++ reg32_write(0x3c0803c8,0x4444); ++ reg32_write(0x3c0803cc,0x8888); ++ reg32_write(0x3c0803d0,0x5665); ++ reg32_write(0x3c0803d4,0x0); ++ reg32_write(0x3c0803d8,0x0); ++ reg32_write(0x3c0803dc,0xf000); ++ reg32_write(0x3c080094,0x0); ++ reg32_write(0x3c0800b4,0x0); ++ reg32_write(0x3c4800b4,0x0); ++ reg32_write(0x3c8800b4,0x0); ++ reg32_write(0x3c08031c,0x21); ++ reg32_write(0x3c48031c,0x21); ++ reg32_write(0x3c88031c,0x21); ++ reg32_write(0x3c080328,0x24); ++ reg32_write(0x3c480328,0x24); ++ reg32_write(0x3c880328,0x24); ++ ++ //enable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); ++ //load the 1D training image ++ ddr_load_train_code(FW_1D_IMAGE); ++ ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xbb8); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); ++ ++ //disable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); ++ //Reset MPU and run ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); ++ wait_ddrphy_training_complete(); ++ ++ //configure DDRPHY-FW DMEM structure @clock1... ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ ++ //set the PHY input clock to the desired frequency for pstate 1 ++ reg32_write(0x3038a008,0x7070000); ++ reg32_write(0x3038a004,0x5000000); ++ reg32_write(0x3038a088,0x7070000); ++ reg32_write(0x3038a084,0x2010000); ++ reg32_write(0x303a00ec,0xffff); ++ tmp=reg32_read(0x303a00f8); ++ tmp |= 0x20; ++ reg32_write(0x303a00f8,tmp); ++ reg32_write(0x30389804,0x1000000); ++ ++ //enable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); ++ //load the 1D training image ++ ddr_load_train_code(FW_1D_IMAGE); ++ ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x84); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x84); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x8400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x8400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); ++ ++ //disable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); ++ //Reset MPU and run ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); ++ wait_ddrphy_training_complete(); ++ ++ //configure DDRPHY-FW DMEM structure @clock2... ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ ++ //set the PHY input clock to the desired frequency for pstate 2 ++ reg32_write(0x3038a008,0x7070000); ++ reg32_write(0x3038a004,0x2000000); ++ reg32_write(0x3038a088,0x7070000); ++ reg32_write(0x3038a084,0x2010000); ++ reg32_write(0x303a00ec,0xffff); ++ tmp=reg32_read(0x303a00f8); ++ tmp |= 0x20; ++ reg32_write(0x303a00f8,tmp); ++ reg32_write(0x30389804,0x1000000); ++ ++ //enable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); ++ //load the 1D training image ++ ddr_load_train_code(FW_1D_IMAGE); ++ ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x84); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x84); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x8400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x8400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); ++ ++ //disable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); ++ //Reset MPU and run ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); ++ wait_ddrphy_training_complete(); ++ ++ //set the PHY input clock to the desired frequency for pstate 0 ++ reg32_write(0x3038a088,0x7070000); ++ reg32_write(0x3038a084,0x4030000); ++ reg32_write(0x303a00ec,0xffff); ++ tmp=reg32_read(0x303a00f8); ++ tmp |= 0x20; ++ reg32_write(0x303a00f8,tmp); ++ reg32_write(0x30360054,0xfa080); ++ reg32_write(0x30360058,0x0); ++ tmp=reg32_read(0x30360050); ++ tmp |= 0x200; ++ reg32_write(0x30360050,tmp); ++ tmp=reg32_read(0x30360050); ++ tmp &= ~0x10; ++ reg32_write(0x30360050,tmp); ++ do{ ++ tmp=reg32_read(0x30360050); ++ if(tmp&0x80000000) break; ++ }while(1); ++ reg32_write(0x30389808,0x1000000); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ ++ ++ //enable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); ++ //load the 2D training image ++ ddr_load_train_code(FW_2D_IMAGE); ++ ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xbb8); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400f,0x100); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54010,0x1f7f); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); ++ ++ //disable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); ++ //Reset MPU and run ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); ++ wait_ddrphy_training_complete(); ++ ++ //Halt MPU ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); ++ //enable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); ++ ++ //Load firmware PIE image ++ reg32_write(0x3c240000,0x10); ++ reg32_write(0x3c240004,0x400); ++ reg32_write(0x3c240008,0x10e); ++ reg32_write(0x3c24000c,0x0); ++ reg32_write(0x3c240010,0x0); ++ reg32_write(0x3c240014,0x8); ++ reg32_write(0x3c2400a4,0xb); ++ reg32_write(0x3c2400a8,0x480); ++ reg32_write(0x3c2400ac,0x109); ++ reg32_write(0x3c2400b0,0x8); ++ reg32_write(0x3c2400b4,0x448); ++ reg32_write(0x3c2400b8,0x139); ++ reg32_write(0x3c2400bc,0x8); ++ reg32_write(0x3c2400c0,0x478); ++ reg32_write(0x3c2400c4,0x109); ++ reg32_write(0x3c2400c8,0x0); ++ reg32_write(0x3c2400cc,0xe8); ++ reg32_write(0x3c2400d0,0x109); ++ reg32_write(0x3c2400d4,0x2); ++ reg32_write(0x3c2400d8,0x10); ++ reg32_write(0x3c2400dc,0x139); ++ reg32_write(0x3c2400e0,0xf); ++ reg32_write(0x3c2400e4,0x7c0); ++ reg32_write(0x3c2400e8,0x139); ++ reg32_write(0x3c2400ec,0x44); ++ reg32_write(0x3c2400f0,0x630); ++ reg32_write(0x3c2400f4,0x159); ++ reg32_write(0x3c2400f8,0x14f); ++ reg32_write(0x3c2400fc,0x630); ++ reg32_write(0x3c240100,0x159); ++ reg32_write(0x3c240104,0x47); ++ reg32_write(0x3c240108,0x630); ++ reg32_write(0x3c24010c,0x149); ++ reg32_write(0x3c240110,0x4f); ++ reg32_write(0x3c240114,0x630); ++ reg32_write(0x3c240118,0x179); ++ reg32_write(0x3c24011c,0x8); ++ reg32_write(0x3c240120,0xe0); ++ reg32_write(0x3c240124,0x109); ++ reg32_write(0x3c240128,0x0); ++ reg32_write(0x3c24012c,0x7c8); ++ reg32_write(0x3c240130,0x109); ++ reg32_write(0x3c240134,0x0); ++ reg32_write(0x3c240138,0x1); ++ reg32_write(0x3c24013c,0x8); ++ reg32_write(0x3c240140,0x0); ++ reg32_write(0x3c240144,0x45a); ++ reg32_write(0x3c240148,0x9); ++ reg32_write(0x3c24014c,0x0); ++ reg32_write(0x3c240150,0x448); ++ reg32_write(0x3c240154,0x109); ++ reg32_write(0x3c240158,0x40); ++ reg32_write(0x3c24015c,0x630); ++ reg32_write(0x3c240160,0x179); ++ reg32_write(0x3c240164,0x1); ++ reg32_write(0x3c240168,0x618); ++ reg32_write(0x3c24016c,0x109); ++ reg32_write(0x3c240170,0x40c0); ++ reg32_write(0x3c240174,0x630); ++ reg32_write(0x3c240178,0x149); ++ reg32_write(0x3c24017c,0x8); ++ reg32_write(0x3c240180,0x4); ++ reg32_write(0x3c240184,0x48); ++ reg32_write(0x3c240188,0x4040); ++ reg32_write(0x3c24018c,0x630); ++ reg32_write(0x3c240190,0x149); ++ reg32_write(0x3c240194,0x0); ++ reg32_write(0x3c240198,0x4); ++ reg32_write(0x3c24019c,0x48); ++ reg32_write(0x3c2401a0,0x40); ++ reg32_write(0x3c2401a4,0x630); ++ reg32_write(0x3c2401a8,0x149); ++ reg32_write(0x3c2401ac,0x10); ++ reg32_write(0x3c2401b0,0x4); ++ reg32_write(0x3c2401b4,0x18); ++ reg32_write(0x3c2401b8,0x0); ++ reg32_write(0x3c2401bc,0x4); ++ reg32_write(0x3c2401c0,0x78); ++ reg32_write(0x3c2401c4,0x549); ++ reg32_write(0x3c2401c8,0x630); ++ reg32_write(0x3c2401cc,0x159); ++ reg32_write(0x3c2401d0,0xd49); ++ reg32_write(0x3c2401d4,0x630); ++ reg32_write(0x3c2401d8,0x159); ++ reg32_write(0x3c2401dc,0x94a); ++ reg32_write(0x3c2401e0,0x630); ++ reg32_write(0x3c2401e4,0x159); ++ reg32_write(0x3c2401e8,0x441); ++ reg32_write(0x3c2401ec,0x630); ++ reg32_write(0x3c2401f0,0x149); ++ reg32_write(0x3c2401f4,0x42); ++ reg32_write(0x3c2401f8,0x630); ++ reg32_write(0x3c2401fc,0x149); ++ reg32_write(0x3c240200,0x1); ++ reg32_write(0x3c240204,0x630); ++ reg32_write(0x3c240208,0x149); ++ reg32_write(0x3c24020c,0x0); ++ reg32_write(0x3c240210,0xe0); ++ reg32_write(0x3c240214,0x109); ++ reg32_write(0x3c240218,0xa); ++ reg32_write(0x3c24021c,0x10); ++ reg32_write(0x3c240220,0x109); ++ reg32_write(0x3c240224,0x9); ++ reg32_write(0x3c240228,0x3c0); ++ reg32_write(0x3c24022c,0x149); ++ reg32_write(0x3c240230,0x9); ++ reg32_write(0x3c240234,0x3c0); ++ reg32_write(0x3c240238,0x159); ++ reg32_write(0x3c24023c,0x18); ++ reg32_write(0x3c240240,0x10); ++ reg32_write(0x3c240244,0x109); ++ reg32_write(0x3c240248,0x0); ++ reg32_write(0x3c24024c,0x3c0); ++ reg32_write(0x3c240250,0x109); ++ reg32_write(0x3c240254,0x18); ++ reg32_write(0x3c240258,0x4); ++ reg32_write(0x3c24025c,0x48); ++ reg32_write(0x3c240260,0x18); ++ reg32_write(0x3c240264,0x4); ++ reg32_write(0x3c240268,0x58); ++ reg32_write(0x3c24026c,0xa); ++ reg32_write(0x3c240270,0x10); ++ reg32_write(0x3c240274,0x109); ++ reg32_write(0x3c240278,0x2); ++ reg32_write(0x3c24027c,0x10); ++ reg32_write(0x3c240280,0x109); ++ reg32_write(0x3c240284,0x5); ++ reg32_write(0x3c240288,0x7c0); ++ reg32_write(0x3c24028c,0x109); ++ reg32_write(0x3c240290,0x10); ++ reg32_write(0x3c240294,0x10); ++ reg32_write(0x3c240298,0x109); ++ reg32_write(0x3c100000,0x811); ++ reg32_write(0x3c100080,0x880); ++ reg32_write(0x3c100100,0x0); ++ reg32_write(0x3c100180,0x0); ++ reg32_write(0x3c100004,0x4008); ++ reg32_write(0x3c100084,0x83); ++ reg32_write(0x3c100104,0x4f); ++ reg32_write(0x3c100184,0x0); ++ reg32_write(0x3c100008,0x4040); ++ reg32_write(0x3c100088,0x83); ++ reg32_write(0x3c100108,0x51); ++ reg32_write(0x3c100188,0x0); ++ reg32_write(0x3c10000c,0x811); ++ reg32_write(0x3c10008c,0x880); ++ reg32_write(0x3c10010c,0x0); ++ reg32_write(0x3c10018c,0x0); ++ reg32_write(0x3c100010,0x720); ++ reg32_write(0x3c100090,0xf); ++ reg32_write(0x3c100110,0x1740); ++ reg32_write(0x3c100190,0x0); ++ reg32_write(0x3c100014,0x16); ++ reg32_write(0x3c100094,0x83); ++ reg32_write(0x3c100114,0x4b); ++ reg32_write(0x3c100194,0x0); ++ reg32_write(0x3c100018,0x716); ++ reg32_write(0x3c100098,0xf); ++ reg32_write(0x3c100118,0x2001); ++ reg32_write(0x3c100198,0x0); ++ reg32_write(0x3c10001c,0x716); ++ reg32_write(0x3c10009c,0xf); ++ reg32_write(0x3c10011c,0x2800); ++ reg32_write(0x3c10019c,0x0); ++ reg32_write(0x3c100020,0x716); ++ reg32_write(0x3c1000a0,0xf); ++ reg32_write(0x3c100120,0xf00); ++ reg32_write(0x3c1001a0,0x0); ++ reg32_write(0x3c100024,0x720); ++ reg32_write(0x3c1000a4,0xf); ++ reg32_write(0x3c100124,0x1400); ++ reg32_write(0x3c1001a4,0x0); ++ reg32_write(0x3c100028,0xe08); ++ reg32_write(0x3c1000a8,0xc15); ++ reg32_write(0x3c100128,0x0); ++ reg32_write(0x3c1001a8,0x0); ++ reg32_write(0x3c10002c,0x623); ++ reg32_write(0x3c1000ac,0x15); ++ reg32_write(0x3c10012c,0x0); ++ reg32_write(0x3c1001ac,0x0); ++ reg32_write(0x3c100030,0x4028); ++ reg32_write(0x3c1000b0,0x80); ++ reg32_write(0x3c100130,0x0); ++ reg32_write(0x3c1001b0,0x0); ++ reg32_write(0x3c100034,0xe08); ++ reg32_write(0x3c1000b4,0xc1a); ++ reg32_write(0x3c100134,0x0); ++ reg32_write(0x3c1001b4,0x0); ++ reg32_write(0x3c100038,0x623); ++ reg32_write(0x3c1000b8,0x1a); ++ reg32_write(0x3c100138,0x0); ++ reg32_write(0x3c1001b8,0x0); ++ reg32_write(0x3c10003c,0x4040); ++ reg32_write(0x3c1000bc,0x80); ++ reg32_write(0x3c10013c,0x0); ++ reg32_write(0x3c1001bc,0x0); ++ reg32_write(0x3c100040,0x2604); ++ reg32_write(0x3c1000c0,0x15); ++ reg32_write(0x3c100140,0x0); ++ reg32_write(0x3c1001c0,0x0); ++ reg32_write(0x3c100044,0x708); ++ reg32_write(0x3c1000c4,0x5); ++ reg32_write(0x3c100144,0x0); ++ reg32_write(0x3c1001c4,0x2002); ++ reg32_write(0x3c100048,0x8); ++ reg32_write(0x3c1000c8,0x80); ++ reg32_write(0x3c100148,0x0); ++ reg32_write(0x3c1001c8,0x0); ++ reg32_write(0x3c10004c,0x2604); ++ reg32_write(0x3c1000cc,0x1a); ++ reg32_write(0x3c10014c,0x0); ++ reg32_write(0x3c1001cc,0x0); ++ reg32_write(0x3c100050,0x708); ++ reg32_write(0x3c1000d0,0xa); ++ reg32_write(0x3c100150,0x0); ++ reg32_write(0x3c1001d0,0x2002); ++ reg32_write(0x3c100054,0x4040); ++ reg32_write(0x3c1000d4,0x80); ++ reg32_write(0x3c100154,0x0); ++ reg32_write(0x3c1001d4,0x0); ++ reg32_write(0x3c100058,0x60a); ++ reg32_write(0x3c1000d8,0x15); ++ reg32_write(0x3c100158,0x1200); ++ reg32_write(0x3c1001d8,0x0); ++ reg32_write(0x3c10005c,0x61a); ++ reg32_write(0x3c1000dc,0x15); ++ reg32_write(0x3c10015c,0x1300); ++ reg32_write(0x3c1001dc,0x0); ++ reg32_write(0x3c100060,0x60a); ++ reg32_write(0x3c1000e0,0x1a); ++ reg32_write(0x3c100160,0x1200); ++ reg32_write(0x3c1001e0,0x0); ++ reg32_write(0x3c100064,0x642); ++ reg32_write(0x3c1000e4,0x1a); ++ reg32_write(0x3c100164,0x1300); ++ reg32_write(0x3c1001e4,0x0); ++ reg32_write(0x3c100068,0x4808); ++ reg32_write(0x3c1000e8,0x880); ++ reg32_write(0x3c100168,0x0); ++ reg32_write(0x3c1001e8,0x0); ++ reg32_write(0x3c24029c,0x0); ++ reg32_write(0x3c2402a0,0x790); ++ reg32_write(0x3c2402a4,0x11a); ++ reg32_write(0x3c2402a8,0x8); ++ reg32_write(0x3c2402ac,0x7aa); ++ reg32_write(0x3c2402b0,0x2a); ++ reg32_write(0x3c2402b4,0x10); ++ reg32_write(0x3c2402b8,0x7b2); ++ reg32_write(0x3c2402bc,0x2a); ++ reg32_write(0x3c2402c0,0x0); ++ reg32_write(0x3c2402c4,0x7c8); ++ reg32_write(0x3c2402c8,0x109); ++ reg32_write(0x3c2402cc,0x10); ++ reg32_write(0x3c2402d0,0x2a8); ++ reg32_write(0x3c2402d4,0x129); ++ reg32_write(0x3c2402d8,0x8); ++ reg32_write(0x3c2402dc,0x370); ++ reg32_write(0x3c2402e0,0x129); ++ reg32_write(0x3c2402e4,0xa); ++ reg32_write(0x3c2402e8,0x3c8); ++ reg32_write(0x3c2402ec,0x1a9); ++ reg32_write(0x3c2402f0,0xc); ++ reg32_write(0x3c2402f4,0x408); ++ reg32_write(0x3c2402f8,0x199); ++ reg32_write(0x3c2402fc,0x14); ++ reg32_write(0x3c240300,0x790); ++ reg32_write(0x3c240304,0x11a); ++ reg32_write(0x3c240308,0x8); ++ reg32_write(0x3c24030c,0x4); ++ reg32_write(0x3c240310,0x18); ++ reg32_write(0x3c240314,0xe); ++ reg32_write(0x3c240318,0x408); ++ reg32_write(0x3c24031c,0x199); ++ reg32_write(0x3c240320,0x8); ++ reg32_write(0x3c240324,0x8568); ++ reg32_write(0x3c240328,0x108); ++ reg32_write(0x3c24032c,0x18); ++ reg32_write(0x3c240330,0x790); ++ reg32_write(0x3c240334,0x16a); ++ reg32_write(0x3c240338,0x8); ++ reg32_write(0x3c24033c,0x1d8); ++ reg32_write(0x3c240340,0x169); ++ reg32_write(0x3c240344,0x10); ++ reg32_write(0x3c240348,0x8558); ++ reg32_write(0x3c24034c,0x168); ++ reg32_write(0x3c240350,0x70); ++ reg32_write(0x3c240354,0x788); ++ reg32_write(0x3c240358,0x16a); ++ reg32_write(0x3c24035c,0x1ff8); ++ reg32_write(0x3c240360,0x85a8); ++ reg32_write(0x3c240364,0x1e8); ++ reg32_write(0x3c240368,0x50); ++ reg32_write(0x3c24036c,0x798); ++ reg32_write(0x3c240370,0x16a); ++ reg32_write(0x3c240374,0x60); ++ reg32_write(0x3c240378,0x7a0); ++ reg32_write(0x3c24037c,0x16a); ++ reg32_write(0x3c240380,0x8); ++ reg32_write(0x3c240384,0x8310); ++ reg32_write(0x3c240388,0x168); ++ reg32_write(0x3c24038c,0x8); ++ reg32_write(0x3c240390,0xa310); ++ reg32_write(0x3c240394,0x168); ++ reg32_write(0x3c240398,0xa); ++ reg32_write(0x3c24039c,0x408); ++ reg32_write(0x3c2403a0,0x169); ++ reg32_write(0x3c2403a4,0x6e); ++ reg32_write(0x3c2403a8,0x0); ++ reg32_write(0x3c2403ac,0x68); ++ reg32_write(0x3c2403b0,0x0); ++ reg32_write(0x3c2403b4,0x408); ++ reg32_write(0x3c2403b8,0x169); ++ reg32_write(0x3c2403bc,0x0); ++ reg32_write(0x3c2403c0,0x8310); ++ reg32_write(0x3c2403c4,0x168); ++ reg32_write(0x3c2403c8,0x0); ++ reg32_write(0x3c2403cc,0xa310); ++ reg32_write(0x3c2403d0,0x168); ++ reg32_write(0x3c2403d4,0x1ff8); ++ reg32_write(0x3c2403d8,0x85a8); ++ reg32_write(0x3c2403dc,0x1e8); ++ reg32_write(0x3c2403e0,0x68); ++ reg32_write(0x3c2403e4,0x798); ++ reg32_write(0x3c2403e8,0x16a); ++ reg32_write(0x3c2403ec,0x78); ++ reg32_write(0x3c2403f0,0x7a0); ++ reg32_write(0x3c2403f4,0x16a); ++ reg32_write(0x3c2403f8,0x68); ++ reg32_write(0x3c2403fc,0x790); ++ reg32_write(0x3c240400,0x16a); ++ reg32_write(0x3c240404,0x8); ++ reg32_write(0x3c240408,0x8b10); ++ reg32_write(0x3c24040c,0x168); ++ reg32_write(0x3c240410,0x8); ++ reg32_write(0x3c240414,0xab10); ++ reg32_write(0x3c240418,0x168); ++ reg32_write(0x3c24041c,0xa); ++ reg32_write(0x3c240420,0x408); ++ reg32_write(0x3c240424,0x169); ++ reg32_write(0x3c240428,0x58); ++ reg32_write(0x3c24042c,0x0); ++ reg32_write(0x3c240430,0x68); ++ reg32_write(0x3c240434,0x0); ++ reg32_write(0x3c240438,0x408); ++ reg32_write(0x3c24043c,0x169); ++ reg32_write(0x3c240440,0x0); ++ reg32_write(0x3c240444,0x8b10); ++ reg32_write(0x3c240448,0x168); ++ reg32_write(0x3c24044c,0x0); ++ reg32_write(0x3c240450,0xab10); ++ reg32_write(0x3c240454,0x168); ++ reg32_write(0x3c240458,0x0); ++ reg32_write(0x3c24045c,0x1d8); ++ reg32_write(0x3c240460,0x169); ++ reg32_write(0x3c240464,0x80); ++ reg32_write(0x3c240468,0x790); ++ reg32_write(0x3c24046c,0x16a); ++ reg32_write(0x3c240470,0x18); ++ reg32_write(0x3c240474,0x7aa); ++ reg32_write(0x3c240478,0x6a); ++ reg32_write(0x3c24047c,0xa); ++ reg32_write(0x3c240480,0x0); ++ reg32_write(0x3c240484,0x1e9); ++ reg32_write(0x3c240488,0x8); ++ reg32_write(0x3c24048c,0x8080); ++ reg32_write(0x3c240490,0x108); ++ reg32_write(0x3c240494,0xf); ++ reg32_write(0x3c240498,0x408); ++ reg32_write(0x3c24049c,0x169); ++ reg32_write(0x3c2404a0,0xc); ++ reg32_write(0x3c2404a4,0x0); ++ reg32_write(0x3c2404a8,0x68); ++ reg32_write(0x3c2404ac,0x9); ++ reg32_write(0x3c2404b0,0x0); ++ reg32_write(0x3c2404b4,0x1a9); ++ reg32_write(0x3c2404b8,0x0); ++ reg32_write(0x3c2404bc,0x408); ++ reg32_write(0x3c2404c0,0x169); ++ reg32_write(0x3c2404c4,0x0); ++ reg32_write(0x3c2404c8,0x8080); ++ reg32_write(0x3c2404cc,0x108); ++ reg32_write(0x3c2404d0,0x8); ++ reg32_write(0x3c2404d4,0x7aa); ++ reg32_write(0x3c2404d8,0x6a); ++ reg32_write(0x3c2404dc,0x0); ++ reg32_write(0x3c2404e0,0x8568); ++ reg32_write(0x3c2404e4,0x108); ++ reg32_write(0x3c2404e8,0xb7); ++ reg32_write(0x3c2404ec,0x790); ++ reg32_write(0x3c2404f0,0x16a); ++ reg32_write(0x3c2404f4,0x1f); ++ reg32_write(0x3c2404f8,0x0); ++ reg32_write(0x3c2404fc,0x68); ++ reg32_write(0x3c240500,0x8); ++ reg32_write(0x3c240504,0x8558); ++ reg32_write(0x3c240508,0x168); ++ reg32_write(0x3c24050c,0xf); ++ reg32_write(0x3c240510,0x408); ++ reg32_write(0x3c240514,0x169); ++ reg32_write(0x3c240518,0xc); ++ reg32_write(0x3c24051c,0x0); ++ reg32_write(0x3c240520,0x68); ++ reg32_write(0x3c240524,0x0); ++ reg32_write(0x3c240528,0x408); ++ reg32_write(0x3c24052c,0x169); ++ reg32_write(0x3c240530,0x0); ++ reg32_write(0x3c240534,0x8558); ++ reg32_write(0x3c240538,0x168); ++ reg32_write(0x3c24053c,0x8); ++ reg32_write(0x3c240540,0x3c8); ++ reg32_write(0x3c240544,0x1a9); ++ reg32_write(0x3c240548,0x3); ++ reg32_write(0x3c24054c,0x370); ++ reg32_write(0x3c240550,0x129); ++ reg32_write(0x3c240554,0x20); ++ reg32_write(0x3c240558,0x2aa); ++ reg32_write(0x3c24055c,0x9); ++ reg32_write(0x3c240560,0x0); ++ reg32_write(0x3c240564,0x400); ++ reg32_write(0x3c240568,0x10e); ++ reg32_write(0x3c24056c,0x8); ++ reg32_write(0x3c240570,0xe8); ++ reg32_write(0x3c240574,0x109); ++ reg32_write(0x3c240578,0x0); ++ reg32_write(0x3c24057c,0x8140); ++ reg32_write(0x3c240580,0x10c); ++ reg32_write(0x3c240584,0x10); ++ reg32_write(0x3c240588,0x8138); ++ reg32_write(0x3c24058c,0x10c); ++ reg32_write(0x3c240590,0x8); ++ reg32_write(0x3c240594,0x7c8); ++ reg32_write(0x3c240598,0x101); ++ reg32_write(0x3c24059c,0x8); ++ reg32_write(0x3c2405a0,0x0); ++ reg32_write(0x3c2405a4,0x8); ++ reg32_write(0x3c2405a8,0x8); ++ reg32_write(0x3c2405ac,0x448); ++ reg32_write(0x3c2405b0,0x109); ++ reg32_write(0x3c2405b4,0xf); ++ reg32_write(0x3c2405b8,0x7c0); ++ reg32_write(0x3c2405bc,0x109); ++ reg32_write(0x3c2405c0,0x0); ++ reg32_write(0x3c2405c4,0xe8); ++ reg32_write(0x3c2405c8,0x109); ++ reg32_write(0x3c2405cc,0x47); ++ reg32_write(0x3c2405d0,0x630); ++ reg32_write(0x3c2405d4,0x109); ++ reg32_write(0x3c2405d8,0x8); ++ reg32_write(0x3c2405dc,0x618); ++ reg32_write(0x3c2405e0,0x109); ++ reg32_write(0x3c2405e4,0x8); ++ reg32_write(0x3c2405e8,0xe0); ++ reg32_write(0x3c2405ec,0x109); ++ reg32_write(0x3c2405f0,0x0); ++ reg32_write(0x3c2405f4,0x7c8); ++ reg32_write(0x3c2405f8,0x109); ++ reg32_write(0x3c2405fc,0x8); ++ reg32_write(0x3c240600,0x8140); ++ reg32_write(0x3c240604,0x10c); ++ reg32_write(0x3c240608,0x0); ++ reg32_write(0x3c24060c,0x1); ++ reg32_write(0x3c240610,0x8); ++ reg32_write(0x3c240614,0x8); ++ reg32_write(0x3c240618,0x4); ++ reg32_write(0x3c24061c,0x8); ++ reg32_write(0x3c240620,0x8); ++ reg32_write(0x3c240624,0x7c8); ++ reg32_write(0x3c240628,0x101); ++ reg32_write(0x3c240018,0x0); ++ reg32_write(0x3c24001c,0x0); ++ reg32_write(0x3c240020,0x8); ++ reg32_write(0x3c240024,0x0); ++ reg32_write(0x3c240028,0x0); ++ reg32_write(0x3c24002c,0x0); ++ reg32_write(0x3c34039c,0x400); ++ reg32_write(0x3c24005c,0x0); ++ reg32_write(0x3c24007c,0x2a); ++ reg32_write(0x3c240098,0x6a); ++ reg32_write(0x3c100340,0x0); ++ reg32_write(0x3c100344,0x101); ++ reg32_write(0x3c100348,0x105); ++ reg32_write(0x3c10034c,0x107); ++ reg32_write(0x3c100350,0x10f); ++ reg32_write(0x3c100354,0x202); ++ reg32_write(0x3c100358,0x20a); ++ reg32_write(0x3c10035c,0x20b); ++ reg32_write(0x3c0800e8,0x2); ++ reg32_write(0x3c08002c,0x5d); ++ reg32_write(0x3c080030,0xbb); ++ reg32_write(0x3c080034,0x753); ++ reg32_write(0x3c080038,0x2c); ++ reg32_write(0x3c48002c,0xc); ++ reg32_write(0x3c480030,0x19); ++ reg32_write(0x3c480034,0xfa); ++ reg32_write(0x3c480038,0x10); ++ reg32_write(0x3c88002c,0x3); ++ reg32_write(0x3c880030,0x6); ++ reg32_write(0x3c880034,0x3e); ++ reg32_write(0x3c880038,0x10); ++ reg32_write(0x3c240030,0x0); ++ reg32_write(0x3c240034,0x173); ++ reg32_write(0x3c240038,0x60); ++ reg32_write(0x3c24003c,0x6110); ++ reg32_write(0x3c240040,0x2152); ++ reg32_write(0x3c240044,0xdfbd); ++ reg32_write(0x3c240048,0x60); ++ reg32_write(0x3c24004c,0x6152); ++ reg32_write(0x3c080040,0x5a); ++ reg32_write(0x3c080044,0x3); ++ reg32_write(0x3c480040,0x5a); ++ reg32_write(0x3c480044,0x3); ++ reg32_write(0x3c880040,0x5a); ++ reg32_write(0x3c880044,0x3); ++ reg32_write(0x3c100200,0xe0); ++ reg32_write(0x3c100204,0x12); ++ reg32_write(0x3c100208,0xe0); ++ reg32_write(0x3c10020c,0x12); ++ reg32_write(0x3c100210,0xe0); ++ reg32_write(0x3c100214,0x12); ++ reg32_write(0x3c500200,0xe0); ++ reg32_write(0x3c500204,0x12); ++ reg32_write(0x3c500208,0xe0); ++ reg32_write(0x3c50020c,0x12); ++ reg32_write(0x3c500210,0xe0); ++ reg32_write(0x3c500214,0x12); ++ reg32_write(0x3c900200,0xe0); ++ reg32_write(0x3c900204,0x12); ++ reg32_write(0x3c900208,0xe0); ++ reg32_write(0x3c90020c,0x12); ++ reg32_write(0x3c900210,0xe0); ++ reg32_write(0x3c900214,0x12); ++ reg32_write(0x3c1003f4,0xf); ++ reg32_write(0x3c040044,0x1); ++ reg32_write(0x3c040048,0x1); ++ reg32_write(0x3c04004c,0x180); ++ reg32_write(0x3c040060,0x1); ++ reg32_write(0x3c040008,0x6209); ++ reg32_write(0x3c0402c8,0x1); ++ reg32_write(0x3c0406d0,0x1); ++ reg32_write(0x3c040ad0,0x1); ++ reg32_write(0x3c040ed0,0x1); ++ reg32_write(0x3c0412d0,0x1); ++ reg32_write(0x3c0416d0,0x1); ++ reg32_write(0x3c041ad0,0x1); ++ reg32_write(0x3c041ed0,0x1); ++ reg32_write(0x3c0422d0,0x1); ++ reg32_write(0x3c044044,0x1); ++ reg32_write(0x3c044048,0x1); ++ reg32_write(0x3c04404c,0x180); ++ reg32_write(0x3c044060,0x1); ++ reg32_write(0x3c044008,0x6209); ++ reg32_write(0x3c0442c8,0x1); ++ reg32_write(0x3c0446d0,0x1); ++ reg32_write(0x3c044ad0,0x1); ++ reg32_write(0x3c044ed0,0x1); ++ reg32_write(0x3c0452d0,0x1); ++ reg32_write(0x3c0456d0,0x1); ++ reg32_write(0x3c045ad0,0x1); ++ reg32_write(0x3c045ed0,0x1); ++ reg32_write(0x3c0462d0,0x1); ++ reg32_write(0x3c048044,0x1); ++ reg32_write(0x3c048048,0x1); ++ reg32_write(0x3c04804c,0x180); ++ reg32_write(0x3c048060,0x1); ++ reg32_write(0x3c048008,0x6209); ++ reg32_write(0x3c0482c8,0x1); ++ reg32_write(0x3c0486d0,0x1); ++ reg32_write(0x3c048ad0,0x1); ++ reg32_write(0x3c048ed0,0x1); ++ reg32_write(0x3c0492d0,0x1); ++ reg32_write(0x3c0496d0,0x1); ++ reg32_write(0x3c049ad0,0x1); ++ reg32_write(0x3c049ed0,0x1); ++ reg32_write(0x3c04a2d0,0x1); ++ reg32_write(0x3c04c044,0x1); ++ reg32_write(0x3c04c048,0x1); ++ reg32_write(0x3c04c04c,0x180); ++ reg32_write(0x3c04c060,0x1); ++ reg32_write(0x3c04c008,0x6209); ++ reg32_write(0x3c04c2c8,0x1); ++ reg32_write(0x3c04c6d0,0x1); ++ reg32_write(0x3c04cad0,0x1); ++ reg32_write(0x3c04ced0,0x1); ++ reg32_write(0x3c04d2d0,0x1); ++ reg32_write(0x3c04d6d0,0x1); ++ reg32_write(0x3c04dad0,0x1); ++ reg32_write(0x3c04ded0,0x1); ++ reg32_write(0x3c04e2d0,0x1); ++ reg32_write(0x3c0800e8,0x2); ++ reg32_write(0x3c300200,0x2); ++ //customer Post Train ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x00020010, 0x0000006a); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x0002001d, 0x00000001); ++ /* ++ * CalBusy.0 =1, indicates the calibrator is actively calibrating. ++ * Wait Calibrating done. ++ */ ++ tmp_t = 1; ++ while(tmp_t) { ++ tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x20097); ++ tmp_t = tmp & 0x01; ++ } ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); ++ //disable APB bus to access DDRPHY RAM ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); ++} diff --git a/board/compulab/ucm-imx8m-mini/ddr/helper.c b/board/compulab/ucm-imx8m-mini/ddr/helper.c new file mode 100644 index 0000000..050c87b diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0001-ucm-imx8m-mini-update-CPU-model-printed-parameters.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0001-ucm-imx8m-mini-update-CPU-model-printed-parameters.patch index 521a078..c8f3acb 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0001-ucm-imx8m-mini-update-CPU-model-printed-parameters.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0001-ucm-imx8m-mini-update-CPU-model-printed-parameters.patch @@ -1,7 +1,7 @@ -From 78e8df0c038d7231cff3628d216f0a9a4c67bb5a Mon Sep 17 00:00:00 2001 +From 9a00a0ef365dd6c9b9e7616b37b2d7522162ba38 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 12 Feb 2019 17:51:20 +0200 -Subject: [PATCH 01/14] ucm-imx8m-mini: update CPU/model printed parameters +Subject: [PATCH 01/25] ucm-imx8m-mini: update CPU/model printed parameters Update the startup messages of the CPU and model parameters @@ -25,7 +25,7 @@ index 112345b..899899c 100644 chosen { diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c -index aa541fc..c13c976 100644 +index 111f1e4..0ea375b 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -235,7 +235,11 @@ int print_cpuinfo(void) diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0002-ucm-imx8m-mini-Fix-KConfig-warning.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0002-ucm-imx8m-mini-Fix-KConfig-warning.patch index b68dfe8..ac374c0 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0002-ucm-imx8m-mini-Fix-KConfig-warning.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0002-ucm-imx8m-mini-Fix-KConfig-warning.patch @@ -1,7 +1,7 @@ -From 7be8b06aa70688675cced06c4d8c53cc3fed90ff Mon Sep 17 00:00:00 2001 +From d16771fa30413c39792e4108b173993796eb58fc Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Wed, 13 Feb 2019 08:56:03 +0200 -Subject: [PATCH 02/14] ucm-imx8m-mini: Fix KConfig warning +Subject: [PATCH 02/25] ucm-imx8m-mini: Fix KConfig warning The following compilation warning is generated: choice value used outside its choice group diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0003-ucm-imx8m-mini-enable-status-LED.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0003-ucm-imx8m-mini-enable-status-LED.patch index b70475f..0ed8c77 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0003-ucm-imx8m-mini-enable-status-LED.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0003-ucm-imx8m-mini-enable-status-LED.patch @@ -1,7 +1,7 @@ -From 3114d2dfba612e1135b4f9bb05878b9dd9bf67f5 Mon Sep 17 00:00:00 2001 +From 8e3dada31bb79910d0f5bbf0e5f6f270806ac726 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Wed, 13 Feb 2019 15:04:59 +0200 -Subject: [PATCH 03/14] ucm-imx8m-mini: enable status LED +Subject: [PATCH 03/25] ucm-imx8m-mini: enable status LED Use the status LED feature to turn on the status LED. diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0004-cmd-eeprom-fix-disregarding-of-the-i2c_bus-parameter.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0004-cmd-eeprom-fix-disregarding-of-the-i2c_bus-parameter.patch index 2642022..36aee07 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0004-cmd-eeprom-fix-disregarding-of-the-i2c_bus-parameter.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0004-cmd-eeprom-fix-disregarding-of-the-i2c_bus-parameter.patch @@ -1,7 +1,7 @@ -From c538d92855cf83445e83a37a08f842f3207499d0 Mon Sep 17 00:00:00 2001 +From f70346c777ec784380d52448507348f411746dc3 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 19 Feb 2019 09:59:20 +0200 -Subject: [PATCH 04/14] cmd: eeprom: fix disregarding of the i2c_bus parameter +Subject: [PATCH 04/25] cmd: eeprom: fix disregarding of the i2c_bus parameter The eeprom commands are disregarding the i2c_bus parameter if CONFIG_SYS_I2C_EEPROM_BUS is defined - setting the i2c bus to diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0005-eeprom-layout-remove-buf-from-the-eeprom_field-struc.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0005-eeprom-layout-remove-buf-from-the-eeprom_field-struc.patch index 493b9fc..3a9994d 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0005-eeprom-layout-remove-buf-from-the-eeprom_field-struc.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0005-eeprom-layout-remove-buf-from-the-eeprom_field-struc.patch @@ -1,7 +1,7 @@ -From c16f56067c09834866aaa965dfd1c5cbf06b603d Mon Sep 17 00:00:00 2001 +From a30ba71e11fa5e187676bc5f011a3fffa6b4b231 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Mon, 18 Sep 2017 19:49:32 +0300 -Subject: [PATCH 05/14] eeprom: layout: remove buf from the eeprom_field +Subject: [PATCH 05/25] eeprom: layout: remove buf from the eeprom_field structure The layout structure contains a pointer to a buffer that contain the diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0006-eeprom-layout-add-field-functions-read.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0006-eeprom-layout-add-field-functions-read.patch index 74f7f0d..9cf3004 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0006-eeprom-layout-add-field-functions-read.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0006-eeprom-layout-add-field-functions-read.patch @@ -1,7 +1,7 @@ -From 134bf3f61fd30ca72bce7c3071e2abce9c0d6edb Mon Sep 17 00:00:00 2001 +From f674928e7c1ea9481a84f8947e39a48cbcb47a1e Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 19 Sep 2017 10:07:26 +0300 -Subject: [PATCH 06/14] eeprom: layout: add field functions read +Subject: [PATCH 06/25] eeprom: layout: add field functions read Read option is missing in the EEPROM layout feature diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0007-compulab-eeprom-layout-add-read-serial-function.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0007-compulab-eeprom-layout-add-read-serial-function.patch index d9d94cc..f35cce7 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0007-compulab-eeprom-layout-add-read-serial-function.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0007-compulab-eeprom-layout-add-read-serial-function.patch @@ -1,7 +1,7 @@ -From 95b4ee8527681bb87043d21030031aa67f5e3f4b Mon Sep 17 00:00:00 2001 +From facb5b85fc780601e4a5aa648d75dcf0715f3740 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 19 Sep 2017 10:47:25 +0300 -Subject: [PATCH 07/14] compulab: eeprom: layout: add read serial function +Subject: [PATCH 07/25] compulab: eeprom: layout: add read serial function The function conver the CompuLab serial number format to tag_serialnr structure. diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0008-compulab-eeprom-layout-support-layout-version-4.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0008-compulab-eeprom-layout-support-layout-version-4.patch index 19e802e..0512604 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0008-compulab-eeprom-layout-support-layout-version-4.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0008-compulab-eeprom-layout-support-layout-version-4.patch @@ -1,7 +1,7 @@ -From ec8e40aed261929bd5a3d75b1aebbe51b9135d76 Mon Sep 17 00:00:00 2001 +From 72c0d9691cfd1f0ca2c420d2ddf72f2067c1462f Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Wed, 29 Nov 2017 10:58:36 +0200 -Subject: [PATCH 08/14] compulab: eeprom: layout: support layout version 4 +Subject: [PATCH 08/25] compulab: eeprom: layout: support layout version 4 Add fields table for layout version 4. Update the code to support layout version 4. diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0009-compulab-integrate-DM_I2C-in-EEPROM-driver.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0009-compulab-integrate-DM_I2C-in-EEPROM-driver.patch index a0eab2d..5fa2d62 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0009-compulab-integrate-DM_I2C-in-EEPROM-driver.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0009-compulab-integrate-DM_I2C-in-EEPROM-driver.patch @@ -1,7 +1,7 @@ -From 90446b34c4f1fdd7b075d09adc0c2516d3ebe1d1 Mon Sep 17 00:00:00 2001 +From 9586611891d34c18ae961f423880e23333a8c8ea Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 19 Feb 2019 18:11:45 +0200 -Subject: [PATCH 09/14] compulab: integrate DM_I2C in EEPROM driver +Subject: [PATCH 09/25] compulab: integrate DM_I2C in EEPROM driver CompuLab's EEPROM driver is enabled only for CONFIG_SYS_I2C. Update the enabling condition of the driver to CONFIG_SYS_I2C or diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0010-i2c-prevent-dual-functions-with-CONFIG_DM_I2C_COMPAT.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0010-i2c-prevent-dual-functions-with-CONFIG_DM_I2C_COMPAT.patch index 3ba1a92..3f01f86 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0010-i2c-prevent-dual-functions-with-CONFIG_DM_I2C_COMPAT.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0010-i2c-prevent-dual-functions-with-CONFIG_DM_I2C_COMPAT.patch @@ -1,7 +1,7 @@ -From 9434b759151b62d5a2b33de2b55274a6b9df89e3 Mon Sep 17 00:00:00 2001 +From 5071f70211f3019c8c9642d83e45d259dacf1d9f Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 19 Feb 2019 18:22:40 +0200 -Subject: [PATCH 10/14] i2c: prevent dual functions with CONFIG_DM_I2C_COMPAT +Subject: [PATCH 10/25] i2c: prevent dual functions with CONFIG_DM_I2C_COMPAT Dual definition of functions exists when CONFIG_DM_I2C_COMPAT is enabled. diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0011-ucm-imx8m-mini-add-support-for-eeprom-layout-comands.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0011-ucm-imx8m-mini-add-support-for-eeprom-layout-comands.patch index eee12b9..39e267a 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0011-ucm-imx8m-mini-add-support-for-eeprom-layout-comands.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0011-ucm-imx8m-mini-add-support-for-eeprom-layout-comands.patch @@ -1,7 +1,7 @@ -From a42b0c1a6dbdbfc0f8b2c373afa83fa15fbe8e7d Mon Sep 17 00:00:00 2001 +From 65e0b15c35ea91fb40569aeacd46a56bfc9fe912 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 19 Feb 2019 18:48:29 +0200 -Subject: [PATCH 11/14] ucm-imx8m-mini: add support for eeprom layout comands +Subject: [PATCH 11/25] ucm-imx8m-mini: add support for eeprom layout comands Add support for EEPROM and EEPROM layout commands for the UCM-iMX8M-Mini. diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0012-mx8m-mini-set-Ethernet-MAC-address-environment.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0012-mx8m-mini-set-Ethernet-MAC-address-environment.patch index a5293fd..5d35e34 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0012-mx8m-mini-set-Ethernet-MAC-address-environment.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0012-mx8m-mini-set-Ethernet-MAC-address-environment.patch @@ -1,7 +1,7 @@ -From 52ea4c51a1b294c2e315679b7069ca230427a37e Mon Sep 17 00:00:00 2001 +From 7990034c06db7a525a7d45a1095ac7ea9cf90a12 Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 19 Feb 2019 21:46:54 +0200 -Subject: [PATCH 12/14] mx8m-mini: set Ethernet MAC address environment +Subject: [PATCH 12/25] mx8m-mini: set Ethernet MAC address environment If the environment variable "ethaddr" is empty: * Read the MAC address from the EEPROM. diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0013-ucm-imx8m-mini-release-U-Boot-v2018.03-ucm-imx8m-min.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0013-ucm-imx8m-mini-release-U-Boot-v2018.03-ucm-imx8m-min.patch index 2cc87cd..53dfd9c 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0013-ucm-imx8m-mini-release-U-Boot-v2018.03-ucm-imx8m-min.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0013-ucm-imx8m-mini-release-U-Boot-v2018.03-ucm-imx8m-min.patch @@ -1,7 +1,7 @@ -From b4e5fdb1856f56ba65981f8a611f71504484b686 Mon Sep 17 00:00:00 2001 +From ee5512ff4b37793e82a035e705bb80758466265a Mon Sep 17 00:00:00 2001 From: Uri Mashiach Date: Tue, 12 Feb 2019 13:50:09 +0200 -Subject: [PATCH 13/14] ucm-imx8m-mini: release U-Boot +Subject: [PATCH 13/25] ucm-imx8m-mini: release U-Boot v2018.03-ucm-imx8m-mini-1.0 Release U-Boot v2018.03-ucm-imx8m-mini-1.0 diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0014-ucm-imx8m-mini-config-Remove-unused-stuff.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0014-ucm-imx8m-mini-config-Remove-unused-stuff.patch index ac993fc..369c846 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0014-ucm-imx8m-mini-config-Remove-unused-stuff.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0014-ucm-imx8m-mini-config-Remove-unused-stuff.patch @@ -1,7 +1,7 @@ -From c78472e670850c7ea7f98a977ef86885eb4c2d97 Mon Sep 17 00:00:00 2001 +From 31c05913ba70ca95119ee279d44e3f229672f67c Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Wed, 20 Feb 2019 08:21:05 +0200 -Subject: [PATCH 14/14] ucm-imx8m-mini: config: Remove unused stuff +Subject: [PATCH 14/25] ucm-imx8m-mini: config: Remove unused stuff Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0015-ucm-imx8m-mini-Enable-uart4-for-bluetooth.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0015-ucm-imx8m-mini-Enable-uart4-for-bluetooth.patch index cc89492..a96dabe 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0015-ucm-imx8m-mini-Enable-uart4-for-bluetooth.patch +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0015-ucm-imx8m-mini-Enable-uart4-for-bluetooth.patch @@ -1,7 +1,7 @@ -From 27f60a15fa94b861363138abf75bec4726a30bc3 Mon Sep 17 00:00:00 2001 +From f49b2cd4dae2efffbf8ea71647484fa0eda278e4 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Thu, 7 Mar 2019 14:17:42 +0200 -Subject: [PATCH 15/15] ucm-imx8m-mini: Enable uart4 for bluetooth +Subject: [PATCH 15/25] ucm-imx8m-mini: Enable uart4 for bluetooth Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0016-ucm-imx8m-mini-ddr-Validate-new-setting.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0016-ucm-imx8m-mini-ddr-Validate-new-setting.patch new file mode 100644 index 0000000..1aadc31 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0016-ucm-imx8m-mini-ddr-Validate-new-setting.patch @@ -0,0 +1,328 @@ +From 48d258e75cd0f0ff0cb68f5173741b91941a8ab4 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Tue, 26 Mar 2019 10:36:45 +0200 +Subject: [PATCH 16/25] ucm-imx8m-mini: ddr: Validate new setting + +Signed-off-by: Valentin Raevsky +--- + board/compulab/ucm-imx8m-mini/ddr/ddr_init.c | 23 +++--- + board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c | 96 ++++++++++++------------ + 2 files changed, 62 insertions(+), 57 deletions(-) + +diff --git a/board/compulab/ucm-imx8m-mini/ddr/ddr_init.c b/board/compulab/ucm-imx8m-mini/ddr/ddr_init.c +index 6093d1b..b3f82ad 100644 +--- a/board/compulab/ucm-imx8m-mini/ddr/ddr_init.c ++++ b/board/compulab/ucm-imx8m-mini/ddr/ddr_init.c +@@ -35,6 +35,11 @@ volatile unsigned int tmp, tmp_t, i; + void ddr_init(void) + { + /** Initialize DDR clock and DDRC registers **/ ++ reg32_write(0x3033023c,0x0); ++ reg32_write(0x30330240,0x0); ++ reg32_write(0x303304a4,0xe); ++ reg32_write(0x303304a8,0xe); ++ reg32_write(0x303304fc,0x0); + reg32_write(0x30391000,0x8f00003f); + reg32_write(0x30391000,0x8f00000f); + reg32_write(0x3038a088,0x7070000); +@@ -61,12 +66,12 @@ void ddr_init(void) + reg32_write(0x3d400030,0x1); + reg32_write(0x3d400000,0xa3080020); + reg32_write(0x3d400020,0x223); +- reg32_write(0x3d400024,0x16e3600); ++ reg32_write(0x3d400024,0x3a980); + reg32_write(0x3d400064,0x5b00d2); + reg32_write(0x3d4000d0,0xc00305ba); + reg32_write(0x3d4000d4,0x940000); + reg32_write(0x3d4000dc,0xd4002d); +- reg32_write(0x3d4000e0,0x310008); ++ reg32_write(0x3d4000e0,0x310000); + reg32_write(0x3d4000e8,0x66004d); + reg32_write(0x3d4000ec,0x16004d); + reg32_write(0x3d400100,0x191e1920); +@@ -92,8 +97,8 @@ void ddr_init(void) + reg32_write(0x3d4001b0,0x11); + reg32_write(0x3d4001c0,0x1); + reg32_write(0x3d4001c4,0x0); +- reg32_write(0x3d4000f4,0x639); +- reg32_write(0x3d400108,0x70e1213); ++ reg32_write(0x3d4000f4,0xc99); ++ reg32_write(0x3d400108,0x70e1617); + reg32_write(0x3d400200,0x16); + reg32_write(0x3d40020c,0x0); + reg32_write(0x3d400210,0x1f1f); +@@ -112,11 +117,11 @@ void ddr_init(void) + reg32_write(0x3d40049c,0x1100e07); + reg32_write(0x3d4004a0,0xc8012c); + reg32_write(0x3d402020,0x21); +- reg32_write(0x3d402024,0x30d400); ++ reg32_write(0x3d402024,0x7d00); + reg32_write(0x3d402050,0x20d040); + reg32_write(0x3d402064,0xc001c); + reg32_write(0x3d4020dc,0x840000); +- reg32_write(0x3d4020e0,0x310008); ++ reg32_write(0x3d4020e0,0x310000); + reg32_write(0x3d4020e8,0x66004d); + reg32_write(0x3d4020ec,0x16004d); + reg32_write(0x3d402100,0xa040305); +@@ -136,11 +141,11 @@ void ddr_init(void) + reg32_write(0x3d402194,0x80303); + reg32_write(0x3d4021b4,0x100); + reg32_write(0x3d403020,0x21); +- reg32_write(0x3d403024,0xc3500); ++ reg32_write(0x3d403024,0x1f40); + reg32_write(0x3d403050,0x20d040); + reg32_write(0x3d403064,0x30007); + reg32_write(0x3d4030dc,0x840000); +- reg32_write(0x3d4030e0,0x310008); ++ reg32_write(0x3d4030e0,0x310000); + reg32_write(0x3d4030e8,0x66004d); + reg32_write(0x3d4030ec,0x16004d); + reg32_write(0x3d403100,0xa010102); +@@ -252,4 +257,4 @@ void ddr_init(void) + /* enable DDR auto-refresh mode */ + tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; + reg32_write(DDRC_RFSHCTL3(0), tmp); +-} ++} +\ No newline at end of file +diff --git a/board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c b/board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c +index 8116069..e4577e0 100644 +--- a/board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c ++++ b/board/compulab/ucm-imx8m-mini/ddr/ddrphy_train.c +@@ -61,11 +61,11 @@ void ddr_cfg_phy(void) { + reg32_write(0x3c240810,0x0); + reg32_write(0x3c640810,0x0); + reg32_write(0x3ca40810,0x0); +- reg32_write(0x3c080090,0xab); ++ reg32_write(0x3c080090,0x1ab); + reg32_write(0x3c0800e8,0x0); +- reg32_write(0x3c480090,0xab); ++ reg32_write(0x3c480090,0x1ab); + reg32_write(0x3c0800e8,0x0); +- reg32_write(0x3c880090,0xab); ++ reg32_write(0x3c880090,0x1ab); + reg32_write(0x3c0800e8,0x0); + reg32_write(0x3c080158,0x3); + reg32_write(0x3c480158,0xa); +@@ -94,30 +94,30 @@ void ddr_cfg_phy(void) { + reg32_write(0x3c848534,0xe00); + reg32_write(0x3c84c134,0xe00); + reg32_write(0x3c84c534,0xe00); +- reg32_write(0x3c040124,0xfbe); +- reg32_write(0x3c040524,0xfbe); +- reg32_write(0x3c044124,0xfbe); +- reg32_write(0x3c044524,0xfbe); +- reg32_write(0x3c048124,0xfbe); +- reg32_write(0x3c048524,0xfbe); +- reg32_write(0x3c04c124,0xfbe); +- reg32_write(0x3c04c524,0xfbe); +- reg32_write(0x3c440124,0xfbe); +- reg32_write(0x3c440524,0xfbe); +- reg32_write(0x3c444124,0xfbe); +- reg32_write(0x3c444524,0xfbe); +- reg32_write(0x3c448124,0xfbe); +- reg32_write(0x3c448524,0xfbe); +- reg32_write(0x3c44c124,0xfbe); +- reg32_write(0x3c44c524,0xfbe); +- reg32_write(0x3c840124,0xfbe); +- reg32_write(0x3c840524,0xfbe); +- reg32_write(0x3c844124,0xfbe); +- reg32_write(0x3c844524,0xfbe); +- reg32_write(0x3c848124,0xfbe); +- reg32_write(0x3c848524,0xfbe); +- reg32_write(0x3c84c124,0xfbe); +- reg32_write(0x3c84c524,0xfbe); ++ reg32_write(0x3c040124,0xeba); ++ reg32_write(0x3c040524,0xeba); ++ reg32_write(0x3c044124,0xeba); ++ reg32_write(0x3c044524,0xeba); ++ reg32_write(0x3c048124,0xeba); ++ reg32_write(0x3c048524,0xeba); ++ reg32_write(0x3c04c124,0xeba); ++ reg32_write(0x3c04c524,0xeba); ++ reg32_write(0x3c440124,0xeba); ++ reg32_write(0x3c440524,0xeba); ++ reg32_write(0x3c444124,0xeba); ++ reg32_write(0x3c444524,0xeba); ++ reg32_write(0x3c448124,0xeba); ++ reg32_write(0x3c448524,0xeba); ++ reg32_write(0x3c44c124,0xeba); ++ reg32_write(0x3c44c524,0xeba); ++ reg32_write(0x3c840124,0xeba); ++ reg32_write(0x3c840524,0xeba); ++ reg32_write(0x3c844124,0xeba); ++ reg32_write(0x3c844524,0xeba); ++ reg32_write(0x3c848124,0xeba); ++ reg32_write(0x3c848524,0xeba); ++ reg32_write(0x3c84c124,0xeba); ++ reg32_write(0x3c84c524,0xeba); + reg32_write(0x3c00010c,0x63); + reg32_write(0x3c00410c,0x63); + reg32_write(0x3c00810c,0x63); +@@ -194,7 +194,7 @@ void ddr_cfg_phy(void) { + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xbb8); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2228); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); +@@ -204,25 +204,25 @@ void ddr_cfg_phy(void) { + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + +@@ -256,7 +256,7 @@ void ddr_cfg_phy(void) { + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x101); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x190); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2228); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); +@@ -266,25 +266,25 @@ void ddr_cfg_phy(void) { + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x84); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x84); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x8400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x8400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + +@@ -318,7 +318,7 @@ void ddr_cfg_phy(void) { + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54002,0x102); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0x64); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2228); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x121f); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); +@@ -328,25 +328,25 @@ void ddr_cfg_phy(void) { + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x84); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x84); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0x8400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x3100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0x8400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x3100); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + +@@ -388,7 +388,7 @@ void ddr_cfg_phy(void) { + + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54003,0xbb8); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54004,0x2); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x1e28); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54005,0x2228); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54006,0x11); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x61); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); +@@ -399,25 +399,25 @@ void ddr_cfg_phy(void) { + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d66); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d00); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); +- reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); ++ reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); + +@@ -1041,4 +1041,4 @@ void ddr_cfg_phy(void) { + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x2006e, 0x0); + //disable APB bus to access DDRPHY RAM + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); +-} ++} +\ No newline at end of file +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0017-ucm-imx8m-mini-defconfig-Disable-CONFIG_NXP_TMU.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0017-ucm-imx8m-mini-defconfig-Disable-CONFIG_NXP_TMU.patch new file mode 100644 index 0000000..2f6a506 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0017-ucm-imx8m-mini-defconfig-Disable-CONFIG_NXP_TMU.patch @@ -0,0 +1,25 @@ +From 9a33e936452fb9343a580cddc0ef7b53009fe277 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Wed, 27 Mar 2019 13:28:51 +0200 +Subject: [PATCH 17/25] ucm-imx8m-mini: defconfig: Disable CONFIG_NXP_TMU + +Signed-off-by: Valentin Raevsky +--- + configs/ucm-imx8m-mini_defconfig | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/configs/ucm-imx8m-mini_defconfig b/configs/ucm-imx8m-mini_defconfig +index b4a9975..75531ac 100644 +--- a/configs/ucm-imx8m-mini_defconfig ++++ b/configs/ucm-imx8m-mini_defconfig +@@ -53,7 +53,6 @@ CONFIG_DM_REGULATOR_FIXED=y + CONFIG_DM_REGULATOR_GPIO=y + CONFIG_DM_SPI=y + CONFIG_DM_THERMAL=y +-CONFIG_NXP_TMU=y + CONFIG_USB=y + CONFIG_DM_USB=y + CONFIG_USB_EHCI_HCD=y +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0018-ucm-imx8m-mini-config-Update-h-file.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0018-ucm-imx8m-mini-config-Update-h-file.patch new file mode 100644 index 0000000..9055a1b --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0018-ucm-imx8m-mini-config-Update-h-file.patch @@ -0,0 +1,50 @@ +From d3ace7ca397d491c73fa3bb706e24182f3dcbc77 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Mon, 22 Apr 2019 12:06:29 +0300 +Subject: [PATCH 18/25] ucm-imx8m-mini: config : Update h-file + +1) Add a missing include +2) Remove duplications + +Signed-off-by: Valentin Raevsky +--- + include/configs/ucm-imx8m-mini.h | 9 ++------- + 1 file changed, 2 insertions(+), 7 deletions(-) + +diff --git a/include/configs/ucm-imx8m-mini.h b/include/configs/ucm-imx8m-mini.h +index 214dad4..046dc24 100644 +--- a/include/configs/ucm-imx8m-mini.h ++++ b/include/configs/ucm-imx8m-mini.h +@@ -10,6 +10,8 @@ + #include + #include + ++#include "imx_env.h" ++ + #ifdef CONFIG_SECURE_BOOT + #define CONFIG_CSF_SIZE 0x2000 /* 8K region */ + #endif +@@ -244,12 +246,6 @@ + #define CONFIG_SYS_FSL_USDHC_NUM 2 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +-#define CONFIG_DOS_PARTITION +-#define CONFIG_CMD_EXT2 +-#define CONFIG_CMD_EXT4 +-#define CONFIG_CMD_EXT4_WRITE +-#define CONFIG_CMD_FAT +- + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +@@ -279,7 +275,6 @@ + #ifndef CONFIG_SPL_BUILD + #define CONFIG_CMD_USB + #define CONFIG_USB_STORAGE +-#define CONFIG_CMD_EXT2 + #define CONFIG_USBD_HS + + #define CONFIG_CMD_USB_MASS_STORAGE +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0019-ucm-imx8m-mini-spl-Refacoring-ddr_init-call.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0019-ucm-imx8m-mini-spl-Refacoring-ddr_init-call.patch new file mode 100644 index 0000000..0d97260 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0019-ucm-imx8m-mini-spl-Refacoring-ddr_init-call.patch @@ -0,0 +1,47 @@ +From f68e48823aa3451306349b2b42b7260de521b0e7 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Sun, 21 Apr 2019 22:17:20 +0300 +Subject: [PATCH 19/25] ucm-imx8m-mini: spl: Refacoring ddr_init() call + +Signed-off-by: Valentin Raevsky +--- + board/compulab/ucm-imx8m-mini/spl.c | 16 ++++++++-------- + 1 file changed, 8 insertions(+), 8 deletions(-) + +diff --git a/board/compulab/ucm-imx8m-mini/spl.c b/board/compulab/ucm-imx8m-mini/spl.c +index 34f7683..8331835 100644 +--- a/board/compulab/ucm-imx8m-mini/spl.c ++++ b/board/compulab/ucm-imx8m-mini/spl.c +@@ -22,21 +22,21 @@ + + #ifdef CONFIG_UCM_IMX8M_LPDDR4 + #include +-#else /* CONFIG_UCM_IMX8M_LPDDR4_VAL */ ++static void __dram_init(void) { ++ ddr_init(&dram_timing); ++} ++#else + #include "ddr/ddr.h" ++static void __dram_init(void) { ++ ddr_init(); ++} + #endif + + DECLARE_GLOBAL_DATA_PTR; + + void spl_dram_init(void) + { +-#ifdef CONFIG_UCM_IMX8M_LPDDR4 +- /* ddr train */ +- ddr_init(&lpddr4_timing); +-#else /* CONFIG_UCM_IMX8M_LPDDR4_VAL */ +- /* ddr train */ +- ddr_init(); +-#endif ++ __dram_init(); + } + + #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0020-ucm-imx8m-mini-Kconfig-Refacoring-ddr-init-config-op.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0020-ucm-imx8m-mini-Kconfig-Refacoring-ddr-init-config-op.patch new file mode 100644 index 0000000..9ca56ac --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0020-ucm-imx8m-mini-Kconfig-Refacoring-ddr-init-config-op.patch @@ -0,0 +1,36 @@ +From 47dc5593e0fac92ff62082ccb0fd4ce818204f1e Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Sun, 21 Apr 2019 22:19:27 +0300 +Subject: [PATCH 20/25] ucm-imx8m-mini: Kconfig: Refacoring ddr init config + option + +Signed-off-by: Valentin Raevsky +--- + board/compulab/ucm-imx8m-mini/Kconfig | 7 +++++-- + 1 file changed, 5 insertions(+), 2 deletions(-) + +diff --git a/board/compulab/ucm-imx8m-mini/Kconfig b/board/compulab/ucm-imx8m-mini/Kconfig +index 1da11b2..e6b3341 100644 +--- a/board/compulab/ucm-imx8m-mini/Kconfig ++++ b/board/compulab/ucm-imx8m-mini/Kconfig +@@ -16,12 +16,15 @@ choice + DDR4 configuration approach + + config UCM_IMX8M_LPDDR4 +- bool "DDR4_INIT_EVK" ++ bool "UCM_IMX8M_LPDDR4" ++ select IMX8MM ++ select SUPPORT_SPL ++ select IMX8M_LPDDR4 + help + imx8mm_evk board configuration approach + + config UCM_IMX8M_LPDDR4_VAL +- bool "DDR4_INIT_VAL" ++ bool "UCM_IMX8M_LPDDR4_VAL" + help + imx8mm_val board configuration approach + +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0021-ucm-imx8m-mini-Makefile-Refacoring-ddr-init-build-op.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0021-ucm-imx8m-mini-Makefile-Refacoring-ddr-init-build-op.patch new file mode 100644 index 0000000..9fbfaa8 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0021-ucm-imx8m-mini-Makefile-Refacoring-ddr-init-build-op.patch @@ -0,0 +1,30 @@ +From d83db5bb0ca12a7d374099424c60b511d809c15e Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Sun, 21 Apr 2019 22:20:29 +0300 +Subject: [PATCH 21/25] ucm-imx8m-mini: Makefile: Refacoring ddr init build + option + +Signed-off-by: Valentin Raevsky +--- + board/compulab/ucm-imx8m-mini/Makefile | 7 ++----- + 1 file changed, 2 insertions(+), 5 deletions(-) + +diff --git a/board/compulab/ucm-imx8m-mini/Makefile b/board/compulab/ucm-imx8m-mini/Makefile +index b092c28..02d3393 100644 +--- a/board/compulab/ucm-imx8m-mini/Makefile ++++ b/board/compulab/ucm-imx8m-mini/Makefile +@@ -8,9 +8,6 @@ obj-y += ucm-imx8m-mini.o + + ifdef CONFIG_SPL_BUILD + obj-y += spl.o +-ifdef UCM_CONFIG_IMX8M_LPDDR4 +-obj-y += lpddr4_timing.o +-else +-obj-y += ddr/ +-endif ++obj-$(CONFIG_UCM_IMX8M_LPDDR4) += lpddr4_timing.o ++obj-$(CONFIG_UCM_IMX8M_LPDDR4_VAL) += ddr/ + endif +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0022-ucm-imx8m-mini-lpddr4_timing-Add-ucm-imx8m-mini-supp.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0022-ucm-imx8m-mini-lpddr4_timing-Add-ucm-imx8m-mini-supp.patch new file mode 100644 index 0000000..e3c165f --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0022-ucm-imx8m-mini-lpddr4_timing-Add-ucm-imx8m-mini-supp.patch @@ -0,0 +1,128 @@ +From a0f46186089019084987f4f22054bb36b9e2e68c Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Wed, 24 Apr 2019 13:55:44 +0300 +Subject: [PATCH 22/25] ucm-imx8m-mini: lpddr4_timing: Add ucm-imx8m-mini + support + +Signed-off-by: Valentin Raevsky +--- + board/compulab/ucm-imx8m-mini/lpddr4_timing.c | 47 +++++++++++++++------------ + 1 file changed, 26 insertions(+), 21 deletions(-) + +diff --git a/board/compulab/ucm-imx8m-mini/lpddr4_timing.c b/board/compulab/ucm-imx8m-mini/lpddr4_timing.c +index 72ba6ee..dfd68ea 100644 +--- a/board/compulab/ucm-imx8m-mini/lpddr4_timing.c ++++ b/board/compulab/ucm-imx8m-mini/lpddr4_timing.c +@@ -4,39 +4,44 @@ + * SPDX-License-Identifier: GPL-2.0+ + */ + #include +-#include ++#include ++#include + #include + #include + ++#undef LPDDR4_CS ++#define LPDDR4_CS 0x3 ++ + struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /* Start to config, default 3200mbps */ + { DDRC_DBG1(0), 0x00000001 }, + { DDRC_PWRCTL(0), 0x00000001 }, +- { DDRC_MSTR(0), 0xa1080020 }, ++ { DDRC_MSTR(0), 0xa3080020 }, + { DDRC_RFSHTMG(0), 0x005b00d2 }, +- { DDRC_INIT0(0), 0xC003061B }, +- { DDRC_INIT1(0), 0x009D0000 }, ++ { DDRC_INIT0(0), 0xC00305BA }, ++ { DDRC_INIT1(0), 0x00940000 }, + { DDRC_INIT3(0), 0x00D4002D }, + { DDRC_INIT4(0), (LPDDR4_MR3 << 16) | 0x0000 }, +- { DDRC_INIT6(0), 0x0066004a }, +- { DDRC_INIT7(0), 0x0006004a }, ++ { DDRC_INIT6(0), 0x0066004d }, ++ { DDRC_INIT7(0), 0x0016004d }, + +- { DDRC_DRAMTMG0(0), 0x1A201B22 }, +- { DDRC_DRAMTMG1(0), 0x00060633 }, +- { DDRC_DRAMTMG3(0), 0x00C0C000 }, +- { DDRC_DRAMTMG4(0), 0x0F04080F }, ++ { DDRC_DRAMTMG0(0), 0x191e1920 }, ++ { DDRC_DRAMTMG1(0), 0x00060630 }, ++ { DDRC_DRAMTMG2(0), 0x070e1617}, ++ { DDRC_DRAMTMG3(0), 0x00b0b000}, ++ { DDRC_DRAMTMG4(0), 0x0e04080e}, + { DDRC_DRAMTMG5(0), 0x02040C0C }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x00000401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0C100002 }, +- { DDRC_DRAMTMG14(0), 0x000000E6 }, +- { DDRC_DRAMTMG17(0), 0x00A00050 }, +- ++ { DDRC_DRAMTMG14(0), 0x000000d8 }, ++ { DDRC_DRAMTMG17(0), 0x0096004b }, ++ + { DDRC_ZQCTL0(0), 0x03200018 }, + { DDRC_ZQCTL1(0), 0x028061A8 }, + { DDRC_ZQCTL2(0), 0x00000000 }, +- ++ + { DDRC_DFITMG0(0), 0x0497820A }, + { DDRC_DFITMG2(0), 0x0000170A }, + { DDRC_DRAMTMG2(0), 0x070E171a }, +@@ -47,19 +52,19 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = { + { DDRC_DFIUPD1(0), 0x00DF00E4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x00000011 }, +- ++ + { DDRC_DFIPHYMSTR(0), 0x00000000 }, + { DDRC_RANKCTL(0), 0x00000c99 }, + + /* address mapping */ +- { DDRC_ADDRMAP0(0), 0x0000001f }, ++ { DDRC_ADDRMAP0(0), 0x00000016 }, + { DDRC_ADDRMAP1(0), 0x00080808 }, + { DDRC_ADDRMAP2(0), 0x00000000 }, + { DDRC_ADDRMAP3(0), 0x00000000 }, + { DDRC_ADDRMAP4(0), 0x00001f1f }, + { DDRC_ADDRMAP5(0), 0x07070707 }, +- { DDRC_ADDRMAP6(0), 0x07070707 }, +- { DDRC_ADDRMAP7(0), 0x00000f0f }, ++ { DDRC_ADDRMAP6(0), 0x0f070707 }, ++ { DDRC_ADDRMAP7(0), 0x00000000 }, + + /* performance setting */ + { DDRC_SCHED(0), 0x29001701 }, +@@ -84,7 +89,7 @@ struct dram_cfg_param lpddr4_ddrc_cfg[] = { + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e }, +- { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 }, ++ { DDRC_FREQ1_DRAMTMG14(0), 0x0000001d }, + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b }, + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 }, +@@ -1766,7 +1771,7 @@ struct dram_cfg_param lpddr4_phy_pie[] = { + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, +- { 0x9015c, 0xe8 }, ++ { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, +@@ -1966,7 +1971,7 @@ struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + }; + + /* lpddr4 timing config params on EVK board */ +-struct dram_timing_info lpddr4_timing = { ++struct dram_timing_info dram_timing = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0023-ucm-imx8m-mini-config-Enable-the-new-LPDDR4-config.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0023-ucm-imx8m-mini-config-Enable-the-new-LPDDR4-config.patch new file mode 100644 index 0000000..b71abd4 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0023-ucm-imx8m-mini-config-Enable-the-new-LPDDR4-config.patch @@ -0,0 +1,25 @@ +From 49aaae221364c9098291921ea411a6613ce4a632 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Wed, 1 May 2019 13:48:53 +0300 +Subject: [PATCH 23/25] ucm-imx8m-mini: config: Enable the new LPDDR4 config + +Signed-off-by: Valentin Raevsky +--- + configs/ucm-imx8m-mini_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/ucm-imx8m-mini_defconfig b/configs/ucm-imx8m-mini_defconfig +index 75531ac..d45e789 100644 +--- a/configs/ucm-imx8m-mini_defconfig ++++ b/configs/ucm-imx8m-mini_defconfig +@@ -3,6 +3,7 @@ CONFIG_ARCH_IMX8M=y + CONFIG_SYS_TEXT_BASE=0x40200000 + CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_TARGET_UCM_IMX8M_MINI=y ++CONFIG_UCM_IMX8M_LPDDR4=y + CONFIG_SPL_MMC_SUPPORT=y + CONFIG_DEFAULT_DEVICE_TREE="ucm-imx8m-mini" + CONFIG_FIT=y +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0024-ucm-imx8m-mini-Move-FS-support-to-defconfig.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0024-ucm-imx8m-mini-Move-FS-support-to-defconfig.patch new file mode 100644 index 0000000..e7d9709 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0024-ucm-imx8m-mini-Move-FS-support-to-defconfig.patch @@ -0,0 +1,53 @@ +From 0aa7bd123bce8038f7c1098ff75cbace4f027825 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Tue, 30 Apr 2019 11:32:58 +0300 +Subject: [PATCH 24/25] ucm-imx8m-mini: Move FS support to defconfig + +Signed-off-by: Valentin Raevsky +--- + configs/ucm-imx8m-mini_defconfig | 5 ++++- + include/configs/ucm-imx8m-mini.h | 6 ------ + 2 files changed, 4 insertions(+), 7 deletions(-) + +diff --git a/configs/ucm-imx8m-mini_defconfig b/configs/ucm-imx8m-mini_defconfig +index d45e789..3bce614 100644 +--- a/configs/ucm-imx8m-mini_defconfig ++++ b/configs/ucm-imx8m-mini_defconfig +@@ -29,8 +29,12 @@ CONFIG_CMD_I2C=y + CONFIG_CMD_CACHE=y + # CONFIG_CMD_LED is not set + CONFIG_CMD_REGULATOR=y ++CONFIG_CMD_EXT2=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y + CONFIG_CMD_FS_GENERIC=y + CONFIG_EFI_PARTITION=y ++CONFIG_PARTITION_TYPE_GUID=y + CONFIG_OF_CONTROL=y + CONFIG_ENV_IS_IN_MMC=y + CONFIG_DM_GPIO=y +@@ -62,4 +66,3 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" + CONFIG_USB_GADGET_VENDOR_NUM=0x0525 + CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 + CONFIG_SDP_LOADADDR=0x40400000 +-CONFIG_FS_FAT=y +diff --git a/include/configs/ucm-imx8m-mini.h b/include/configs/ucm-imx8m-mini.h +index 046dc24..8b55fd6 100644 +--- a/include/configs/ucm-imx8m-mini.h ++++ b/include/configs/ucm-imx8m-mini.h +@@ -224,12 +224,6 @@ + #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +-#define CONFIG_DOS_PARTITION +-#define CONFIG_CMD_EXT2 +-#define CONFIG_CMD_EXT4 +-#define CONFIG_CMD_EXT4_WRITE +-#define CONFIG_CMD_FAT +- + #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ + #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0025-ucm-imx8m-mini-config-CONFIG_IMX_OPTEE-y.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0025-ucm-imx8m-mini-config-CONFIG_IMX_OPTEE-y.patch new file mode 100644 index 0000000..60d6701 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0025-ucm-imx8m-mini-config-CONFIG_IMX_OPTEE-y.patch @@ -0,0 +1,25 @@ +From 1b5d113f4ad6ff07e1af1381a77eac9bc181da90 Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Wed, 1 May 2019 21:48:56 +0300 +Subject: [PATCH 25/25] ucm-imx8m-mini: config: CONFIG_IMX_OPTEE=y + +Signed-off-by: Valentin Raevsky +--- + configs/ucm-imx8m-mini_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/configs/ucm-imx8m-mini_defconfig b/configs/ucm-imx8m-mini_defconfig +index 3bce614..d457d26 100644 +--- a/configs/ucm-imx8m-mini_defconfig ++++ b/configs/ucm-imx8m-mini_defconfig +@@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 + CONFIG_TARGET_UCM_IMX8M_MINI=y + CONFIG_UCM_IMX8M_LPDDR4=y + CONFIG_SPL_MMC_SUPPORT=y ++CONFIG_IMX_OPTEE=y + CONFIG_DEFAULT_DEVICE_TREE="ucm-imx8m-mini" + CONFIG_FIT=y + CONFIG_SPL_LOAD_FIT=y +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0026-set-extended-temperature-range.patch b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0026-set-extended-temperature-range.patch new file mode 100644 index 0000000..a44c592 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/0026-set-extended-temperature-range.patch @@ -0,0 +1,27 @@ +From 8f8c940a3c2e4fa837a8f86c0d76ecdf962c1898 Mon Sep 17 00:00:00 2001 +From: Kirill Kapranov +Date: Fri, 3 May 2019 23:00:08 +0300 +Subject: [PATCH 3/3] set extended temperature range + +--- + arch/arm/dts/ucm-imx8m-mini.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm/dts/ucm-imx8m-mini.dts b/arch/arm/dts/ucm-imx8m-mini.dts +index 899899c1c6..b7a2cf0afd 100644 +--- a/arch/arm/dts/ucm-imx8m-mini.dts ++++ b/arch/arm/dts/ucm-imx8m-mini.dts +@@ -450,3 +450,10 @@ + &usbotg2 { + status = "disabled"; + }; ++ ++&cpu_alert0 { ++ temperature = <105000>; ++}; ++&cpu_crit0 { ++ temperature = <115000>; ++}; +-- +2.11.0 + diff --git a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/ucm-imx8m-mini_defconfig b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/ucm-imx8m-mini_defconfig index b4a9975..d457d26 100644 --- a/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/ucm-imx8m-mini_defconfig +++ b/meta-bsp-imx8mm/recipes-bsp/u-boot/compulab/imx8mm/ucm-imx8m-mini_defconfig @@ -3,7 +3,9 @@ CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_TARGET_UCM_IMX8M_MINI=y +CONFIG_UCM_IMX8M_LPDDR4=y CONFIG_SPL_MMC_SUPPORT=y +CONFIG_IMX_OPTEE=y CONFIG_DEFAULT_DEVICE_TREE="ucm-imx8m-mini" CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y @@ -28,8 +30,12 @@ CONFIG_CMD_I2C=y CONFIG_CMD_CACHE=y # CONFIG_CMD_LED is not set CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_EFI_PARTITION=y +CONFIG_PARTITION_TYPE_GUID=y CONFIG_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_DM_GPIO=y @@ -53,7 +59,6 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SPI=y CONFIG_DM_THERMAL=y -CONFIG_NXP_TMU=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_EHCI_HCD=y @@ -62,4 +67,3 @@ CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_SDP_LOADADDR=0x40400000 -CONFIG_FS_FAT=y diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm.inc b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm.inc index 5c03916..f9316b6 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm.inc +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm.inc @@ -18,6 +18,16 @@ SRC_URI_append_ucm-imx8m-mini = " \ file://0016-ucm-imx8m-mini-Enable-mipi-dsi-panel-in-device-tree.patch \ file://0017-ucm-imx8m-mini-defconfig-Enable-startek-ili9881c.patch \ file://0018-ucm-imx8m-mini-defconfig-Update-defconfig.patch \ - file://0019-startek-ili9881c-Change-pixel-clock-tom-85M.patch \ + file://0019-startek-ili9881c-Change-pixel-clock-to-62M.patch \ + file://0020-ucm-imx8m-mini-dts-Enable-bluetooth.patch \ + file://0021-ucm-imx8m-mini-Add-analog-audio-support.patch \ + file://0022-ucm-imx8m-mini-dts-Some-small-changes.patch \ + file://0023-ucm-imx8m-mini_defconfig-Enable-wm8731-with-sdma-as-.patch \ + file://0024-ucm-imx8m-mini-defconfig-Enable-CONFIG_FRAMEBUFFER_C.patch \ + file://0025-UCM-iMX8M-Mini-enable-on-CPU-SNVS-RTC-driver.patch \ + file://0026-ucm-imx8m-mini-dts-Fix-eMMC-mode.patch \ + file://0027-ucm-imx8m-mini-Enable-display-backlight-dimming-cont.patch \ + file://0028-Set-an-extended-temperature-range.patch \ + file://0029-dts-Revert-eMMC-compatible-string.patch \ file://defconfig \ " diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0000-ucm-imx8m-mini-add-basic-support.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0000-ucm-imx8m-mini-add-basic-support.patch index 48a610e..731d367 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0000-ucm-imx8m-mini-add-basic-support.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0000-ucm-imx8m-mini-add-basic-support.patch @@ -1,7 +1,7 @@ -From 7734a8c3034d771fb5a77ee40bb4e07beb10af1b Mon Sep 17 00:00:00 2001 +From c4a92b149db3c8090208c0f92cfb810469e49b69 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 5 Feb 2019 11:49:11 +0200 -Subject: [PATCH 00/19] ucm-imx8m-mini: add basic support +Subject: [PATCH 00/25] ucm-imx8m-mini: add basic support Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0001-ov5640_mipi_v2-gpio_set_value_cansleep.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0001-ov5640_mipi_v2-gpio_set_value_cansleep.patch index 5f3aa57..e2cb9a9 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0001-ov5640_mipi_v2-gpio_set_value_cansleep.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0001-ov5640_mipi_v2-gpio_set_value_cansleep.patch @@ -1,7 +1,7 @@ -From a5d3ea86a2398a92a8156ca257c224db8b289f72 Mon Sep 17 00:00:00 2001 +From 414c22df8637cd560ad56d3378bf4400cc7c15ff Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 11:44:48 +0200 -Subject: [PATCH 01/19] ov5640_mipi_v2: gpio_set_value_cansleep +Subject: [PATCH 01/25] ov5640_mipi_v2: gpio_set_value_cansleep Signed-off-by: Valentin Raevsky --- @@ -9,10 +9,10 @@ Signed-off-by: Valentin Raevsky 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/mxc/capture/ov5640_mipi_v2.c b/drivers/media/platform/mxc/capture/ov5640_mipi_v2.c -index 1cb3d69..ffbb06e 100644 +index d681863..3ad0371 100644 --- a/drivers/media/platform/mxc/capture/ov5640_mipi_v2.c +++ b/drivers/media/platform/mxc/capture/ov5640_mipi_v2.c -@@ -504,19 +504,19 @@ static void ov5640_reset(struct ov5640 *sensor) +@@ -536,19 +536,19 @@ static void ov5640_reset(struct ov5640 *sensor) return; /* camera reset */ diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0002-ucm-imx8m-mini-dts-remove-phy-supply.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0002-ucm-imx8m-mini-dts-remove-phy-supply.patch index 0c4f4cd..a365ade 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0002-ucm-imx8m-mini-dts-remove-phy-supply.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0002-ucm-imx8m-mini-dts-remove-phy-supply.patch @@ -1,7 +1,7 @@ -From 07b42f934e40c72e68a0118c4cc1dd98ddf85bd7 Mon Sep 17 00:00:00 2001 +From a00d10cdbc29b9fddaae31ff68ea78d0b8cdbcf0 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 5 Feb 2019 17:39:39 +0200 -Subject: [PATCH 02/19] ucm-imx8m-mini: dts: remove phy-supply +Subject: [PATCH 02/25] ucm-imx8m-mini: dts: remove phy-supply Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0003-ucm-imx8m-mini-dts-Enable-onboard-LED.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0003-ucm-imx8m-mini-dts-Enable-onboard-LED.patch index 556f09b..2e0404d 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0003-ucm-imx8m-mini-dts-Enable-onboard-LED.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0003-ucm-imx8m-mini-dts-Enable-onboard-LED.patch @@ -1,7 +1,7 @@ -From 0508d43fd390d75e2f51b3b32f48d504f2874dbe Mon Sep 17 00:00:00 2001 +From 4b27cd415780d1ff01da4cb13a098c7f9ef9c422 Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Wed, 13 Feb 2019 21:43:15 +0200 -Subject: [PATCH 03/19] ucm-imx8m-mini: dts: Enable onboard LED +Subject: [PATCH 03/25] ucm-imx8m-mini: dts: Enable onboard LED Enable onboard LED and set 'Heartbeat' as its default trigger. diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0004-ucm-imx8m-mini-dts-Fix-CSI-reset-GPIO.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0004-ucm-imx8m-mini-dts-Fix-CSI-reset-GPIO.patch index a20dbeb..76209fe 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0004-ucm-imx8m-mini-dts-Fix-CSI-reset-GPIO.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0004-ucm-imx8m-mini-dts-Fix-CSI-reset-GPIO.patch @@ -1,7 +1,7 @@ -From d3baf889ad637e279d80647b8f81ccf5dd564250 Mon Sep 17 00:00:00 2001 +From 7bdf5b0eb3da6011e7a5b214a43a95b603e61030 Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Sat, 9 Feb 2019 20:15:02 +0200 -Subject: [PATCH 04/19] ucm-imx8m-mini: dts: Fix CSI reset GPIO +Subject: [PATCH 04/25] ucm-imx8m-mini: dts: Fix CSI reset GPIO Fix the camera rst-gpio in accordance with SB-UCM-iMX8 Rev2.0 topology. diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0005-ucm-imx8m-mini-dts-Fix-SD2-properties.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0005-ucm-imx8m-mini-dts-Fix-SD2-properties.patch index dbfc62e..92b96a8 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0005-ucm-imx8m-mini-dts-Fix-SD2-properties.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0005-ucm-imx8m-mini-dts-Fix-SD2-properties.patch @@ -1,7 +1,7 @@ -From 715b6fff2fd242830a0ca2a9719334f1f8035156 Mon Sep 17 00:00:00 2001 +From 2431ba2df8d3637457c63f702cea6572d92959eb Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Sat, 9 Feb 2019 21:05:39 +0200 -Subject: [PATCH 05/19] ucm-imx8m-mini:dts: Fix SD2 properties +Subject: [PATCH 05/25] ucm-imx8m-mini:dts: Fix SD2 properties Define WP GPIO. Add no-1-8-v, that's necessary for some uSD cards. diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0006-sb-ucm-imx8m-rev2.0-dts-Enable-I2C-GPIO-expander.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0006-sb-ucm-imx8m-rev2.0-dts-Enable-I2C-GPIO-expander.patch index e10d4d6..0396f27 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0006-sb-ucm-imx8m-rev2.0-dts-Enable-I2C-GPIO-expander.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0006-sb-ucm-imx8m-rev2.0-dts-Enable-I2C-GPIO-expander.patch @@ -1,7 +1,7 @@ -From 4f3a2ae13ad565eb8715957928be227ff7f9117e Mon Sep 17 00:00:00 2001 +From 6ef5d7622b35bd4b84b7a368194792690379eb31 Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Sat, 9 Feb 2019 21:40:45 +0200 -Subject: [PATCH 06/19] sb-ucm-imx8m-rev2.0: dts: Enable I2C GPIO expander +Subject: [PATCH 06/25] sb-ucm-imx8m-rev2.0: dts: Enable I2C GPIO expander Enable PCA9555 @i2c1 GPIO expander. i2c1 bus descriptor has been moved to baseboard include file. diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0007-sb-ucm-imx8m-rev2.0-dts-Enable-PCIe.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0007-sb-ucm-imx8m-rev2.0-dts-Enable-PCIe.patch index 7d76ad0..7ead5d0 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0007-sb-ucm-imx8m-rev2.0-dts-Enable-PCIe.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0007-sb-ucm-imx8m-rev2.0-dts-Enable-PCIe.patch @@ -1,7 +1,7 @@ -From 7c184e134a728c7613dbb5b69fe7d455ded1a7af Mon Sep 17 00:00:00 2001 +From 616ee920cdfcfe8b98b6548e7b0c0841c540c0e5 Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Sat, 9 Feb 2019 21:25:15 +0200 -Subject: [PATCH 07/19] sb-ucm-imx8m-rev2.0: dts: Enable PCIe +Subject: [PATCH 07/25] sb-ucm-imx8m-rev2.0: dts: Enable PCIe Enable PCIe0 interface (mini-PCIe connector). diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0008-ucm-imx8m-mini-dts-Enable-onboard-EEPROM.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0008-ucm-imx8m-mini-dts-Enable-onboard-EEPROM.patch index 2d046ae..f746b2a 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0008-ucm-imx8m-mini-dts-Enable-onboard-EEPROM.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0008-ucm-imx8m-mini-dts-Enable-onboard-EEPROM.patch @@ -1,7 +1,7 @@ -From a9a168aa176f2fa581623d5ed700fbee89c2cca6 Mon Sep 17 00:00:00 2001 +From 59efe4700168c99a9b8654e06b821b34cd86fc38 Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Thu, 14 Feb 2019 17:42:19 +0200 -Subject: [PATCH 08/19] ucm-imx8m-mini:dts: Enable onboard EEPROM +Subject: [PATCH 08/25] ucm-imx8m-mini:dts: Enable onboard EEPROM Enable onboard EEPROM type of Atmel 24c08 at 0x50@i2c2. diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0009-sb-ucm-imx8m-rev2.0-dts-Enable-baseboard-EEPROM.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0009-sb-ucm-imx8m-rev2.0-dts-Enable-baseboard-EEPROM.patch index 16094c6..8709596 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0009-sb-ucm-imx8m-rev2.0-dts-Enable-baseboard-EEPROM.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0009-sb-ucm-imx8m-rev2.0-dts-Enable-baseboard-EEPROM.patch @@ -1,7 +1,7 @@ -From acb7558cba2ed9fed8ed4e7eacac8d4f015a99a8 Mon Sep 17 00:00:00 2001 +From 29bc22e8e9964734a80e9caf37e807f191dd7329 Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Sat, 9 Feb 2019 22:17:53 +0200 -Subject: [PATCH 09/19] sb-ucm-imx8m-rev2.0:dts: Enable baseboard EEPROM +Subject: [PATCH 09/25] sb-ucm-imx8m-rev2.0:dts: Enable baseboard EEPROM Enable eeprom type of Atmel 24c08 at 0x54@i2c1. diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0010-ucm-imx8m-mini-Enable-Sterling-LWB5-Wi-Fi-over-SDIO.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0010-ucm-imx8m-mini-Enable-Sterling-LWB5-Wi-Fi-over-SDIO.patch index 4be2af3..a5f65ac 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0010-ucm-imx8m-mini-Enable-Sterling-LWB5-Wi-Fi-over-SDIO.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0010-ucm-imx8m-mini-Enable-Sterling-LWB5-Wi-Fi-over-SDIO.patch @@ -1,7 +1,7 @@ -From 2ee92a8630c5137830efaa49e3f39c2092e3dabb Mon Sep 17 00:00:00 2001 +From 60061b9c12b1e360e7ba26f5a39cf79e96ef826d Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Wed, 13 Feb 2019 22:08:03 +0200 -Subject: [PATCH 10/19] ucm-imx8m-mini: Enable Sterling-LWB5 Wi-Fi over SDIO +Subject: [PATCH 10/25] ucm-imx8m-mini: Enable Sterling-LWB5 Wi-Fi over SDIO Enable Wi-Fi over SDIO using Sterling-LWB5 Dual-Band 802.11ac Wi-Fi + Bluetooth v4.2 Combo Module. diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0011-ucm-imx8m-mini-Enable-touchscreen.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0011-ucm-imx8m-mini-Enable-touchscreen.patch index 9b4ba17..4440c1b 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0011-ucm-imx8m-mini-Enable-touchscreen.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0011-ucm-imx8m-mini-Enable-touchscreen.patch @@ -1,7 +1,7 @@ -From 96bcd898959e09716000ea9160fac0a4a3cf4999 Mon Sep 17 00:00:00 2001 +From f1cefcbdb071e58348cae0adde1b0fbe733da323 Mon Sep 17 00:00:00 2001 From: Kirill Kapranov Date: Sun, 17 Feb 2019 18:21:29 +0200 -Subject: [PATCH 11/19] ucm-imx8m-mini: Enable touchscreen +Subject: [PATCH 11/25] ucm-imx8m-mini: Enable touchscreen Signed-off-by: Kirill Kapranov --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0012-ucm-imx8m-mini-dts-Add-thermal-test-device-tree.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0012-ucm-imx8m-mini-dts-Add-thermal-test-device-tree.patch index e95d9f2..2eb5705 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0012-ucm-imx8m-mini-dts-Add-thermal-test-device-tree.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0012-ucm-imx8m-mini-dts-Add-thermal-test-device-tree.patch @@ -1,7 +1,7 @@ -From c51de10ddfea6e132d384c81f925eca9fac159b9 Mon Sep 17 00:00:00 2001 +From b3029ce50e5b91362b2c2d3af879e83bc0c4c7b3 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 11:46:39 +0200 -Subject: [PATCH 12/19] ucm-imx8m-mini: dts: Add thermal test device tree +Subject: [PATCH 12/25] ucm-imx8m-mini: dts: Add thermal test device tree Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0013-sn65dsi83-Add-ti-sn65dsi83-dsi-to-lvds-bridge-driver.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0013-sn65dsi83-Add-ti-sn65dsi83-dsi-to-lvds-bridge-driver.patch index 6e352a2..21d69b3 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0013-sn65dsi83-Add-ti-sn65dsi83-dsi-to-lvds-bridge-driver.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0013-sn65dsi83-Add-ti-sn65dsi83-dsi-to-lvds-bridge-driver.patch @@ -1,7 +1,7 @@ -From 01cae113925182f248c56c458b0c665a4e861080 Mon Sep 17 00:00:00 2001 +From 7b74defca0f043437550d165ce4e003bd96d592b Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 11:50:09 +0200 -Subject: [PATCH 13/19] sn65dsi83: Add ti,sn65dsi83 dsi to lvds bridge driver +Subject: [PATCH 13/25] sn65dsi83: Add ti,sn65dsi83 dsi to lvds bridge driver Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0014-ucm-imx8m-mini-Enable-lvds-in-device-tree.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0014-ucm-imx8m-mini-Enable-lvds-in-device-tree.patch index 7af1ba1..aabce97 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0014-ucm-imx8m-mini-Enable-lvds-in-device-tree.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0014-ucm-imx8m-mini-Enable-lvds-in-device-tree.patch @@ -1,7 +1,7 @@ -From 322d97f7ddf5c26187cafdcd783ccc284a6a1eaa Mon Sep 17 00:00:00 2001 +From a52d69d2fecd4e13a0d0d85a0f116f80a50fa14e Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 11:51:38 +0200 -Subject: [PATCH 14/19] ucm-imx8m-mini: Enable lvds in device tree +Subject: [PATCH 14/25] ucm-imx8m-mini: Enable lvds in device tree Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0015-startek-ili9881c-Add-panel-driver.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0015-startek-ili9881c-Add-panel-driver.patch index 4f840f6..3db5f94 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0015-startek-ili9881c-Add-panel-driver.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0015-startek-ili9881c-Add-panel-driver.patch @@ -1,7 +1,7 @@ -From 6d3bf971d4e27a4c679c89eb7e0216912efa0a15 Mon Sep 17 00:00:00 2001 +From 5192394d11f57ccd74c3aedcb7689fbf6147280c Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 12:04:29 +0200 -Subject: [PATCH 15/19] startek-ili9881c: Add panel driver +Subject: [PATCH 15/25] startek-ili9881c: Add panel driver Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0016-ucm-imx8m-mini-Enable-mipi-dsi-panel-in-device-tree.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0016-ucm-imx8m-mini-Enable-mipi-dsi-panel-in-device-tree.patch index 7ceefdc..3f21c24 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0016-ucm-imx8m-mini-Enable-mipi-dsi-panel-in-device-tree.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0016-ucm-imx8m-mini-Enable-mipi-dsi-panel-in-device-tree.patch @@ -1,7 +1,7 @@ -From ac548e897f13770fb706c3ceeaf60fcc02ea75a1 Mon Sep 17 00:00:00 2001 +From f8434321ff74e779efc763da881a9a061ee2d057 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 12:12:44 +0200 -Subject: [PATCH 16/19] ucm-imx8m-mini: Enable mipi dsi panel in device tree +Subject: [PATCH 16/25] ucm-imx8m-mini: Enable mipi dsi panel in device tree Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0017-ucm-imx8m-mini-defconfig-Enable-startek-ili9881c.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0017-ucm-imx8m-mini-defconfig-Enable-startek-ili9881c.patch index 91ae6e5..4c9f532 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0017-ucm-imx8m-mini-defconfig-Enable-startek-ili9881c.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0017-ucm-imx8m-mini-defconfig-Enable-startek-ili9881c.patch @@ -1,7 +1,7 @@ -From 8e3b76bce797f09162779a9ed159e49960cb5b97 Mon Sep 17 00:00:00 2001 +From d5e611b869596f08a81694186550a71ea7368bd2 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 15:07:56 +0200 -Subject: [PATCH 17/19] ucm-imx8m-mini: defconfig: Enable startek-ili9881c +Subject: [PATCH 17/25] ucm-imx8m-mini: defconfig: Enable startek-ili9881c Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0018-ucm-imx8m-mini-defconfig-Update-defconfig.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0018-ucm-imx8m-mini-defconfig-Update-defconfig.patch index 64c81be..2d54b46 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0018-ucm-imx8m-mini-defconfig-Update-defconfig.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0018-ucm-imx8m-mini-defconfig-Update-defconfig.patch @@ -1,7 +1,7 @@ -From 30d46158b9a07b5c0fa5ccd4bcc77301ff0bcd86 Mon Sep 17 00:00:00 2001 +From a914b8f5f2caa5a8dd4124f257c193f87a8dd47b Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Tue, 19 Feb 2019 16:26:29 +0200 -Subject: [PATCH 18/19] ucm-imx8m-mini: defconfig: Update defconfig +Subject: [PATCH 18/25] ucm-imx8m-mini: defconfig: Update defconfig Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0019-startek-ili9881c-Change-pixel-clock-tom-85M.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0019-startek-ili9881c-Change-pixel-clock-to-62M.patch similarity index 81% rename from meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0019-startek-ili9881c-Change-pixel-clock-tom-85M.patch rename to meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0019-startek-ili9881c-Change-pixel-clock-to-62M.patch index f6ea0ca..bc5f1af 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0019-startek-ili9881c-Change-pixel-clock-tom-85M.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0019-startek-ili9881c-Change-pixel-clock-to-62M.patch @@ -1,7 +1,7 @@ -From 4613a0f87ecffcaf82a5ed18df8f28694327c406 Mon Sep 17 00:00:00 2001 +From 049096c3dc77e0b59c046cda7cd2b5df7d675564 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Thu, 21 Feb 2019 10:09:23 +0200 -Subject: [PATCH 19/19] startek-ili9881c: Change pixel clock tom 85M +Subject: [PATCH 20/25] startek-ili9881c: Change pixel clock to 62M Signed-off-by: Valentin Raevsky --- @@ -17,7 +17,7 @@ index ca7b7c6..147a594 100644 #define LCD_XSIZE_TFT 720 #define LCD_YSIZE_TFT 1280 -#define PCLOCK 80000 -+#define PCLOCK 85000 ++#define PCLOCK 62000 #define LCD_VBPD 20 #define LCD_VFPD 10 #define LCD_VSPW 10 diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0020-ucm-imx8m-mini-dts-Enable-bluetooth.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0020-ucm-imx8m-mini-dts-Enable-bluetooth.patch index 8918022..5d66997 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0020-ucm-imx8m-mini-dts-Enable-bluetooth.patch +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0020-ucm-imx8m-mini-dts-Enable-bluetooth.patch @@ -1,7 +1,7 @@ -From c4dcb8c1d46c4b754e8b93ced8e0c0dd052d80a6 Mon Sep 17 00:00:00 2001 +From 8c0150a6dbc73e0d2ee60945bf0a4bf2dcf912e6 Mon Sep 17 00:00:00 2001 From: Valentin Raevsky Date: Thu, 7 Mar 2019 13:42:24 +0200 -Subject: [PATCH 20/20] ucm-imx8m-mini: dts: Enable bluetooth +Subject: [PATCH 21/25] ucm-imx8m-mini: dts: Enable bluetooth Signed-off-by: Valentin Raevsky --- diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0021-ucm-imx8m-mini-Add-analog-audio-support.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0021-ucm-imx8m-mini-Add-analog-audio-support.patch new file mode 100644 index 0000000..08977f0 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0021-ucm-imx8m-mini-Add-analog-audio-support.patch @@ -0,0 +1,112 @@ +From 61398457cf72bc14e32ee069da9392b8e6647f8c Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Mon, 15 Apr 2019 07:27:58 +0300 +Subject: [PATCH 22/25] ucm-imx8m-mini: Add analog audio support + +Signed-off-by: Valentin Raevsky +--- + arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts | 67 +++++++++++++++++++++++++ + 1 file changed, 67 insertions(+) + +diff --git a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +index a23bd0b..e1de792 100644 +--- a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts ++++ b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +@@ -113,6 +113,43 @@ + enable-active-high; + vin-supply = <®ulator_bt_reg_on>; + }; ++ ++ simple_sound: sound { ++ compatible = "simple-audio-card"; ++ simple-audio-card,name = "ucm-imx8m-mini"; ++ simple-audio-card,widgets = ++ "Headphone", "Headphone Jack", ++ "Line", "Line Out", ++ "Microphone", "Mic Jack", ++ "Line", "Line In"; ++ simple-audio-card,routing = ++ "Headphone Jack", "RHPOUT", ++ "Headphone Jack", "LHPOUT", ++ "MICIN", "Mic Bias", ++ "Mic Bias", "Mic Jack"; ++ simple-audio-card,format = "i2s"; ++ simple-audio-card,bitclock-master = <&sound_master>; ++ simple-audio-card,frame-master = <&sound_master>; ++ simple-audio-card,bitclock-inversion; ++ ++ sound_master: simple-audio-card,cpu { ++ sound-dai = <&sai2>; ++ system-clock-frequency = <0>; ++ system-clock-direction = "out"; ++ }; ++ ++ sound_codec: simple-audio-card,codec { ++ sound-dai = <&wm8731>; ++ system-clock-direction = "in"; ++ system-clock-type = "mclk"; ++ }; ++ ++ }; ++}; ++ ++&clk { ++ assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; ++ assigned-clock-rates = <786432000>, <722534400>; + }; + + &iomuxc { +@@ -364,6 +401,18 @@ + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; ++ ++ pinctrl_sai2: sai2grp { ++ fsl,pins = < ++ MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 ++ MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 ++ MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0xd6 ++ MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 ++ MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 ++ MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 ++ >; ++ }; ++ + }; + }; + +@@ -550,6 +599,13 @@ + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + ++ wm8731: wm8731@1a { ++ #sound-dai-cells = <0>; ++ compatible = "wlf,wm8731"; ++ reg = <0x1a>; ++ status = "okay"; ++ }; ++ + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + reg = <0x3c>; +@@ -751,6 +807,17 @@ + status = "okay"; + }; + ++&sai2 { ++ #sound-dai-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_sai2>; ++ assigned-clocks = <&clk IMX8MM_CLK_SAI2_SRC>, ++ <&clk IMX8MM_CLK_SAI2_DIV>; ++ assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; ++ assigned-clock-rates = <0>, <12288000>; ++ status = "okay"; ++}; ++ + &lcdif { + status = "okay"; + }; +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0022-ucm-imx8m-mini-dts-Some-small-changes.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0022-ucm-imx8m-mini-dts-Some-small-changes.patch new file mode 100644 index 0000000..34fb469 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0022-ucm-imx8m-mini-dts-Some-small-changes.patch @@ -0,0 +1,53 @@ +From d4344065f5a895dea7823d36fccf2013c4c5247d Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Tue, 30 Apr 2019 15:52:55 +0300 +Subject: [PATCH 23/25] ucm-imx8m-mini: dts: Some small changes + +1) Defibed gpioledgrp ping group. +2) Cahnged GPIO3_IO16 init pad value. + +Signed-off-by: Valentin Raevsky +--- + arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts | 12 +++++++++++- + 1 file changed, 11 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +index e1de792..10cd529 100644 +--- a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts ++++ b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +@@ -28,6 +28,9 @@ + + leds { + compatible = "gpio-leds"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpio_led>; ++ + heartbeat-led { + label = "Heartbeat"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; +@@ -160,7 +163,7 @@ + pinctrl_hog_1: hoggrp-1 { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 +- MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x190 ++ MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 + /* BT */ + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 +@@ -187,6 +190,13 @@ + >; + }; + ++ pinctrl_gpio_led: gpioledgrp { ++ fsl,pins = < ++ MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 ++ >; ++ }; ++ ++ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0023-ucm-imx8m-mini_defconfig-Enable-wm8731-with-sdma-as-.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0023-ucm-imx8m-mini_defconfig-Enable-wm8731-with-sdma-as-.patch new file mode 100644 index 0000000..6a865bb --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0023-ucm-imx8m-mini_defconfig-Enable-wm8731-with-sdma-as-.patch @@ -0,0 +1,35 @@ +From 6550362fd8d95e7db6ab0df2475306d41774e3bb Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Thu, 2 May 2019 16:07:16 +0300 +Subject: [PATCH 24/25] ucm-imx8m-mini_defconfig: Enable wm8731 with sdma as a + module + +Signed-off-by: Valentin Raevsky +--- + arch/arm64/configs/ucm-imx8m-mini_defconfig | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/arm64/configs/ucm-imx8m-mini_defconfig b/arch/arm64/configs/ucm-imx8m-mini_defconfig +index 57d2aee..229fa47 100644 +--- a/arch/arm64/configs/ucm-imx8m-mini_defconfig ++++ b/arch/arm64/configs/ucm-imx8m-mini_defconfig +@@ -355,6 +355,7 @@ CONFIG_SND_SOC_IMX_AMIX=y + CONFIG_SND_SOC_IMX_CDNHDMI=y + CONFIG_SND_SOC_IMX_DSP=y + CONFIG_SND_SOC_AK4613=y ++CONFIG_SND_SOC_WM8731=m + CONFIG_SND_SIMPLE_CARD=y + CONFIG_HID_A4TECH=y + CONFIG_HID_APPLE=y +@@ -446,7 +447,7 @@ CONFIG_RTC_DRV_ABX80X=y + CONFIG_DMADEVICES=y + CONFIG_BCM_SBA_RAID=m + CONFIG_FSL_EDMA_V3=y +-CONFIG_IMX_SDMA=y ++CONFIG_IMX_SDMA=m + CONFIG_MXS_DMA=y + CONFIG_PL330_DMA=y + CONFIG_QCOM_HIDMA_MGMT=y +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0024-ucm-imx8m-mini-defconfig-Enable-CONFIG_FRAMEBUFFER_C.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0024-ucm-imx8m-mini-defconfig-Enable-CONFIG_FRAMEBUFFER_C.patch new file mode 100644 index 0000000..ea94d62 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0024-ucm-imx8m-mini-defconfig-Enable-CONFIG_FRAMEBUFFER_C.patch @@ -0,0 +1,26 @@ +From 425db18c3ada18eef10a7286334357506483f33e Mon Sep 17 00:00:00 2001 +From: Valentin Raevsky +Date: Thu, 2 May 2019 16:57:40 +0300 +Subject: [PATCH 25/25] ucm-imx8m-mini: defconfig: Enable + CONFIG_FRAMEBUFFER_CONSOLE_ROTATION + +Signed-off-by: Valentin Raevsky +--- + arch/arm64/configs/ucm-imx8m-mini_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/ucm-imx8m-mini_defconfig b/arch/arm64/configs/ucm-imx8m-mini_defconfig +index 229fa47..8b95764 100644 +--- a/arch/arm64/configs/ucm-imx8m-mini_defconfig ++++ b/arch/arm64/configs/ucm-imx8m-mini_defconfig +@@ -333,6 +333,7 @@ CONFIG_BACKLIGHT_GENERIC=m + CONFIG_BACKLIGHT_PWM=y + CONFIG_BACKLIGHT_LP855X=y + CONFIG_FRAMEBUFFER_CONSOLE=y ++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y + CONFIG_LOGO=y + CONFIG_SOUND=y + CONFIG_SND=y +-- +1.9.1 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0025-UCM-iMX8M-Mini-enable-on-CPU-SNVS-RTC-driver.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0025-UCM-iMX8M-Mini-enable-on-CPU-SNVS-RTC-driver.patch new file mode 100644 index 0000000..c492d2b --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0025-UCM-iMX8M-Mini-enable-on-CPU-SNVS-RTC-driver.patch @@ -0,0 +1,25 @@ +From eef6e97f7cfbf82aa6b1666ab507134678513e5c Mon Sep 17 00:00:00 2001 +From: Kirill Kapranov +Date: Tue, 19 Mar 2019 12:11:02 +0200 +Subject: [PATCH 1/1] UCM-iMX8M-Mini: enable on-CPU SNVS-RTC driver + +Signed-off-by: Kirill Kapranov +--- + arch/arm64/configs/ucm-imx8m-mini_defconfig | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/configs/ucm-imx8m-mini_defconfig b/arch/arm64/configs/ucm-imx8m-mini_defconfig +index 22b11f10f0dd..da34ab273580 100644 +--- a/arch/arm64/configs/ucm-imx8m-mini_defconfig ++++ b/arch/arm64/configs/ucm-imx8m-mini_defconfig +@@ -443,6 +443,7 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y + CONFIG_LEDS_TRIGGER_CPU=y + CONFIG_RTC_CLASS=y + CONFIG_RTC_DRV_ABX80X=y ++CONFIG_RTC_DRV_SNVS=y + CONFIG_DMADEVICES=y + CONFIG_BCM_SBA_RAID=m + CONFIG_FSL_EDMA_V3=y +-- +2.11.0 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0026-ucm-imx8m-mini-dts-Fix-eMMC-mode.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0026-ucm-imx8m-mini-dts-Fix-eMMC-mode.patch new file mode 100644 index 0000000..ad47cdf --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0026-ucm-imx8m-mini-dts-Fix-eMMC-mode.patch @@ -0,0 +1,29 @@ +From 105a08dfc2a6d5ddccc6e12afa3ab19e3af625be Mon Sep 17 00:00:00 2001 +From: Kirill Kapranov +Date: Wed, 10 Apr 2019 19:01:37 +0300 +Subject: [PATCH 2/3] ucm-imx8m-mini: dts: Fix eMMC mode + +Fix usdhc3 (eMMC) voltage to prevent a corresponding driver to fall back +on legacy bus mode. + +Signed-off-by: Kirill Kapranov +--- + arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts | 1 ++ + 1 file changed, 2 insertion(++) + +diff --git a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +index ab66f04bc34f..34d34501f223 100644 +--- a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts ++++ b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +@@ -636,6 +636,8 @@ + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; ++ no-1-8-v; ++ mmc-ddr-3_3v; + bus-width = <8>; + non-removable; + status = "okay"; +-- +2.11.0 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0027-ucm-imx8m-mini-Enable-display-backlight-dimming-cont.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0027-ucm-imx8m-mini-Enable-display-backlight-dimming-cont.patch new file mode 100644 index 0000000..4576759 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0027-ucm-imx8m-mini-Enable-display-backlight-dimming-cont.patch @@ -0,0 +1,55 @@ +From 3e060d1c0a1e862011aacbb50b22a6411b99594f Mon Sep 17 00:00:00 2001 +From: Kirill Kapranov +Date: Thu, 11 Apr 2019 15:10:19 +0300 +Subject: [PATCH 3/3] ucm-imx8m-mini: Enable display backlight dimming control + +Signed-off-by: Kirill Kapranov +--- + arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +index 34d34501f223..6fa129876eae 100644 +--- a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts ++++ b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +@@ -78,6 +78,15 @@ + enable-active-high; + startup-delay-us = <500>; + }; ++ ++ backlight { ++ compatible = "pwm-backlight"; ++ pwms = <&pwm2 0 3000000 0>; ++ ++ brightness-levels = <0 1 2 4 8 16 32 64 128 255>; ++ default-brightness-level = <9>; ++ status = "okay"; ++ }; + }; + + &iomuxc { +@@ -309,6 +318,11 @@ + MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59 + >; + }; ++ pinctrl_pwm_backlight: pwm_backlightgrp { ++ fsl,pins = < ++ MX8MM_IOMUXC_GPIO1_IO13_PWM2_OUT 0x03 ++ >; ++ }; + }; + }; + +@@ -693,3 +707,9 @@ + status = "okay"; + }; + }; ++ ++&pwm2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_pwm_backlight>; ++ status = "okay"; ++}; +-- +2.11.0 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0028-Set-an-extended-temperature-range.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0028-Set-an-extended-temperature-range.patch new file mode 100644 index 0000000..4729968 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0028-Set-an-extended-temperature-range.patch @@ -0,0 +1,27 @@ +From 646599d79fff3c591a935b3af942bb1fff18e111 Mon Sep 17 00:00:00 2001 +From: Kirill Kapranov +Date: Sun, 5 May 2019 19:06:43 +0300 +Subject: [PATCH 28/28] Set an extended temperature range + +--- + arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +diff --git a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +index 10cd529b0874..be6d0e69c09a 100644 +--- a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts ++++ b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +@@ -842,3 +842,10 @@ + status = "okay"; + }; + }; ++ ++&cpu_alert0 { ++ temperature = <105000>; ++}; ++&cpu_crit0 { ++ temperature = <115000>; ++}; +-- +2.11.0 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0029-dts-Revert-eMMC-compatible-string.patch b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0029-dts-Revert-eMMC-compatible-string.patch new file mode 100644 index 0000000..fcaafc8 --- /dev/null +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/0029-dts-Revert-eMMC-compatible-string.patch @@ -0,0 +1,28 @@ +From 3e3e4f354ee21e6e7242bf2c302d33473a291471 Mon Sep 17 00:00:00 2001 +From: Kirill Kapranov +Date: Tue, 7 May 2019 19:34:21 +0300 +Subject: [PATCH 29/29] dts: Revert eMMC "compatible" string + +Set the "compatible" property for USDHC3 to "fsl,imx7d-usdhc". With this value +eMMC storage works stable. + +Signed-off-by: Kirill Kapranov +--- + arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +index 9854cf5087de..fa6ca04653ba 100644 +--- a/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts ++++ b/arch/arm64/boot/dts/compulab/ucm-imx8m-mini.dts +@@ -785,6 +785,7 @@ + }; + + &usdhc3 { ++ compatible = "fsl,imx8mq-usdhc\0fsl,imx7d-usdhc"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; +-- +2.11.0 + diff --git a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/defconfig b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/defconfig index b84fb89..f693467 100644 --- a/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/defconfig +++ b/meta-bsp-imx8mm/recipes-kernel/linux/compulab/imx8mm/defconfig @@ -1,6 +1,6 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/arm64 4.14.78 Kernel Configuration +# Linux/arm64 4.14.98 Kernel Configuration # CONFIG_ARM64=y CONFIG_64BIT=y @@ -2416,6 +2416,7 @@ CONFIG_I2C_IMX_LPI2C=y # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_PXA_PCI is not set # CONFIG_I2C_RK3X is not set +# CONFIG_I2C_RPBUS is not set # CONFIG_I2C_SIMTEC is not set # CONFIG_I2C_THUNDERX is not set # CONFIG_I2C_XILINX is not set @@ -3450,7 +3451,7 @@ CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y @@ -3722,7 +3723,7 @@ CONFIG_SND_SOC_WM8524=y # CONFIG_SND_SOC_WM8580 is not set # CONFIG_SND_SOC_WM8711 is not set # CONFIG_SND_SOC_WM8728 is not set -# CONFIG_SND_SOC_WM8731 is not set +CONFIG_SND_SOC_WM8731=m # CONFIG_SND_SOC_WM8737 is not set # CONFIG_SND_SOC_WM8741 is not set # CONFIG_SND_SOC_WM8750 is not set @@ -4192,22 +4193,21 @@ CONFIG_MXC_HANTRO_845=y CONFIG_MXC_HANTRO_845_H1=y # -# MXC VPU(Video Processing Unit) MALONE support +# MXC VPU(Video Processing Unit) LEGACY DECODER support +# +# CONFIG_MXC_VPU_LEGACY is not set + +# +# MXC VPU(Video Processing Unit) MALONE DECODER support # CONFIG_MXC_VPU_MALONE=y # CONFIG_MXC_VPU_MALONE_DEBUG is not set # -# MXC VPU(Video Processing Unit) B0 DECODER support +# MXC VPU(Video Processing Unit) WINDSOR ENCODER support # -CONFIG_MXC_VPU_DECODER=y -# CONFIG_MXC_VPU_DECODER_DEBUG is not set - -# -# MXC VPU(Video Processing Unit) B0 ENCODER support -# -CONFIG_MXC_VPU_ENCODER=y -# CONFIG_MXC_VPU_ENCODER_DEBUG is not set +CONFIG_MXC_VPU_WINDSOR=y +# CONFIG_MXC_VPU_WINDSOR_DEBUG is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set @@ -4397,7 +4397,7 @@ CONFIG_DMA_OF=y CONFIG_BCM_SBA_RAID=m # CONFIG_FSL_EDMA is not set CONFIG_FSL_EDMA_V3=y -CONFIG_IMX_SDMA=y +CONFIG_IMX_SDMA=m # CONFIG_INTEL_IDMA64 is not set # CONFIG_MV_XOR_V2 is not set CONFIG_MXS_DMA=y diff --git a/meta-bsp-imx8mm/tools/setup-compulab-env b/meta-bsp-imx8mm/tools/setup-compulab-env index 3f3b920..e322ed0 100755 --- a/meta-bsp-imx8mm/tools/setup-compulab-env +++ b/meta-bsp-imx8mm/tools/setup-compulab-env @@ -22,14 +22,16 @@ cat << eof | tee -a ${BBLAYERS_CONF} > /dev/null BBLAYERS += " \\ \${BSPDIR}/sources/meta-compulab-bsp/meta-bsp-imx8mm \\ \${BSPDIR}/sources/meta-compulab-bsp/meta-desktop \\ + \${BSPDIR}/sources/meta-compulab-bsp/meta-multimedia \\ \${BSPDIR}/sources/meta-compulab \\ + \${BSPDIR}/sources/meta-compulab-bsp/meta-xfce \\ " eof } mod_local() { # Modify local.conf -CORE_IMAGE_EXTRA_INSTALL+=" dhcp-client memtester cl-uboot cl-deploy u-boot-fw-utils" +CORE_IMAGE_EXTRA_INSTALL+=" dhcp-client memtester cl-uboot cl-deploy u-boot-fw-utils bt-start" IMAGE_FEATURES+=" package-management ssh-server-openssh " cat << eof | tee -a ${LOCAL_CONF} > /dev/null CORE_IMAGE_EXTRA_INSTALL += "${CORE_IMAGE_EXTRA_INSTALL}"